diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala
index 9faee504..66af8ef4 100644
--- a/src/main/scala/coreplex/PeripheryBus.scala
+++ b/src/main/scala/coreplex/PeripheryBus.scala
@@ -33,7 +33,7 @@ class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends T
 
   val fromSystemBus: TLInwardNode = {
     val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic))
-    inwardBufNode := atomics.node
+    xbar.node :*= TLBuffer(params.masterBuffering) :*= atomics.node
   }
 
   def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) {
@@ -59,5 +59,5 @@ trait HasPeripheryBus extends HasSystemBus {
   val pbus = LazyModule(new PeripheryBus(pbusParams))
 
   // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
-  pbus.fromSystemBus := sbus.toPeripheryBus()
+  pbus.fromSystemBus :*= sbus.toPeripheryBus()
 }
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 875a8eb0..7bce33da 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -39,7 +39,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   def toSplitSlaves: TLOutwardNode = outwardSplitNode
 
   def toPeripheryBus(addBuffers: Int = 0): TLOutwardNode = {
-    TLBuffer.chain(addBuffers).foldRight(pbus_fixer.node:TLOutwardNode)(_ := _)
+    TLBuffer.chain(addBuffers).foldRight(pbus_fixer.node:TLOutwardNode)(_ :*= _)
   }
 
   val toMemoryBus: TLOutwardNode = outwardNode