riscv/rocket-chip
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Catch bad physical address MSBs when VA size > PA size

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Andrew Waterman 2017-04-13 15:57:57 -07:00 committed by Andrew Waterman
parent 6fbbccca3e
commit fdfcffb0b2
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/TLB.scala
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@ -100,7 +100,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
val do_refill = Bool(usingVM) && io.ptw.resp.valid val do_refill = Bool(usingVM) && io.ptw.resp.valid
val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate)
val mpu_ppn = Mux(do_refill, refill_ppn, val mpu_ppn = Mux(do_refill, refill_ppn,
Mux(vm_enabled, entries.last.ppn, vpn(ppnBits-1, 0))) Mux(vm_enabled, entries.last.ppn, vpn))
val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
val pmp = Module(new PMPChecker(lgMaxSize)) val pmp = Module(new PMPChecker(lgMaxSize))
pmp.io.addr := mpu_physaddr pmp.io.addr := mpu_physaddr