From fdfcffb0b20f96856d8e9906922ff808a2612ff1 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 13 Apr 2017 15:57:57 -0700 Subject: [PATCH] Catch bad physical address MSBs when VA size > PA size --- src/main/scala/rocket/TLB.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index 2daae155..b7a5943e 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -100,7 +100,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters val do_refill = Bool(usingVM) && io.ptw.resp.valid val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) val mpu_ppn = Mux(do_refill, refill_ppn, - Mux(vm_enabled, entries.last.ppn, vpn(ppnBits-1, 0))) + Mux(vm_enabled, entries.last.ppn, vpn)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr