riscv/rocket-chip
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INPUT/OUTPUT orderring swapped

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Huy Vo committed 2012-07-12 18:16:57 -07:00
1 parent bac82762d3
commit fd95159837
17 files changed
+182 -182
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rocket/src/main/scala/ptw.scala
+1 -1
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@@ -75,7 +75,7 @@ class ioPTW(n: Int) extends Bundle
{
val requestor = Vec(n) { new ioTLB_PTW }.flip
val mem = new ioHellaCache
val ptbr = UFix(PADDR_BITS, INPUT)
val ptbr = UFix(INPUT, PADDR_BITS)
}
class rocketPTW(n: Int) extends Component