INPUT/OUTPUT orderring swapped

2012-07-12 18:12:49 -07:00
parent bac82762d3
commit fd95159837
17 changed files with 182 additions and 182 deletions
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@ -75,7 +75,7 @@ class ioPTW(n: Int) extends Bundle
 {
  val requestor = Vec(n) { new ioTLB_PTW }.flip
  val mem   = new ioHellaCache
-  val ptbr  = UFix(PADDR_BITS, INPUT)
+  val ptbr  = UFix(INPUT, PADDR_BITS)
 }

 class rocketPTW(n: Int) extends Component