From fd951598379724bbfc769d75ef29bc4bbf8978ae Mon Sep 17 00:00:00 2001 From: Huy Vo Date: Thu, 12 Jul 2012 18:12:49 -0700 Subject: [PATCH] INPUT/OUTPUT orderring swapped --- rocket/src/main/scala/ctrl.scala | 34 ++++++------- rocket/src/main/scala/ctrl_util.scala | 4 +- rocket/src/main/scala/ctrl_vec.scala | 16 +++---- rocket/src/main/scala/dpath.scala | 8 ++-- rocket/src/main/scala/dpath_alu.scala | 12 ++--- rocket/src/main/scala/dpath_util.scala | 38 +++++++-------- rocket/src/main/scala/dpath_vec.scala | 34 ++++++------- rocket/src/main/scala/dtlb.scala | 4 +- rocket/src/main/scala/fpu.scala | 66 +++++++++++++------------- rocket/src/main/scala/icache.scala | 6 +-- rocket/src/main/scala/itlb.scala | 24 +++++----- rocket/src/main/scala/llc.scala | 14 +++--- rocket/src/main/scala/multiplier.scala | 8 ++-- rocket/src/main/scala/nbdcache.scala | 62 ++++++++++++------------ rocket/src/main/scala/ptw.scala | 2 +- rocket/src/main/scala/queues.scala | 2 +- rocket/src/main/scala/uncore.scala | 30 ++++++------ 17 files changed, 182 insertions(+), 182 deletions(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index fbb05994..2de93962 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -10,7 +10,7 @@ import hwacha._ class ioCtrlDpath extends Bundle() { // outputs to datapath - val sel_pc = UFix(3, OUTPUT); + val sel_pc = UFix(OUTPUT, 3); val wen_btb = Bool(OUTPUT); val clr_btb = Bool(OUTPUT); val stallf = Bool(OUTPUT); @@ -21,16 +21,16 @@ class ioCtrlDpath extends Bundle() val killm = Bool(OUTPUT); val ren2 = Bool(OUTPUT); val ren1 = Bool(OUTPUT); - val sel_alu2 = UFix(3, OUTPUT); + val sel_alu2 = UFix(OUTPUT, 3); val fn_dw = Bool(OUTPUT); - val fn_alu = UFix(4, OUTPUT); + val fn_alu = UFix(OUTPUT, 4); val mul_val = Bool(OUTPUT); - val mul_fn = UFix(2, OUTPUT); + val mul_fn = UFix(OUTPUT, 2); val div_val = Bool(OUTPUT); - val div_fn = UFix(2, OUTPUT); + val div_fn = UFix(OUTPUT, 2); val sel_wa = Bool(OUTPUT); - val sel_wb = UFix(3, OUTPUT); - val pcr = UFix(3, OUTPUT) + val sel_wb = UFix(OUTPUT, 3); + val pcr = UFix(OUTPUT, 3) val id_eret = Bool(OUTPUT); val wb_eret = Bool(OUTPUT); val mem_load = Bool(OUTPUT); @@ -41,16 +41,16 @@ class ioCtrlDpath extends Bundle() val wb_wen = Bool(OUTPUT); val wb_valid = Bool(OUTPUT) val flush_inst = Bool(OUTPUT); - val ex_mem_type = UFix(3,OUTPUT) + val ex_mem_type = UFix(OUTPUT, 3) // exception handling val exception = Bool(OUTPUT); - val cause = UFix(6,OUTPUT); + val cause = UFix(OUTPUT, 6); val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault val vec_irq_aux_wen = Bool(OUTPUT) // inputs from datapath val xcpt_ma_inst = Bool(INPUT); // high on a misaligned/illegal virtual PC val btb_hit = Bool(INPUT); - val inst = Bits(32, INPUT); + val inst = Bits(INPUT, 32); val br_eq = Bool(INPUT); val br_lt = Bool(INPUT); val br_ltu = Bool(INPUT); @@ -59,15 +59,15 @@ class ioCtrlDpath extends Bundle() val mul_rdy = Bool(INPUT); val mul_result_val = Bool(INPUT); val mem_wb = Bool(INPUT); - val ex_waddr = UFix(5,INPUT); // write addr from execute stage - val mem_waddr = UFix(5,INPUT); // write addr from memory stage - val wb_waddr = UFix(5,INPUT); // write addr from writeback stage - val status = Bits(32, INPUT); + val ex_waddr = UFix(INPUT, 5); // write addr from execute stage + val mem_waddr = UFix(INPUT, 5); // write addr from memory stage + val wb_waddr = UFix(INPUT, 5); // write addr from writeback stage + val status = Bits(INPUT, 32); val sboard_clr = Bool(INPUT); - val sboard_clra = UFix(5, INPUT); + val sboard_clra = UFix(INPUT, 5); val fp_sboard_clr = Bool(INPUT); - val fp_sboard_clra = UFix(5, INPUT); - val fp_sboard_wb_waddr = UFix(5, INPUT); + val fp_sboard_clra = UFix(INPUT, 5); + val fp_sboard_wb_waddr = UFix(INPUT, 5); val irq_timer = Bool(INPUT); val irq_ipi = Bool(INPUT); } diff --git a/rocket/src/main/scala/ctrl_util.scala b/rocket/src/main/scala/ctrl_util.scala index 77d855bb..416033a6 100644 --- a/rocket/src/main/scala/ctrl_util.scala +++ b/rocket/src/main/scala/ctrl_util.scala @@ -6,12 +6,12 @@ import Node._; class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component { class read_port extends Bundle { - val addr = UFix(log2Up(entries), INPUT) + val addr = UFix(INPUT, log2Up(entries)) val data = Bool(OUTPUT) } class write_port extends Bundle { val en = Bool(INPUT) - val addr = UFix(log2Up(entries), INPUT) + val addr = UFix(INPUT, log2Up(entries)) val data = Bool(INPUT) } diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala index 7e4d2eec..4fe89d5d 100644 --- a/rocket/src/main/scala/ctrl_vec.scala +++ b/rocket/src/main/scala/ctrl_vec.scala @@ -7,14 +7,14 @@ import Instructions._ class ioCtrlDpathVec extends Bundle { - val inst = Bits(32, INPUT) + val inst = Bits(INPUT, 32) val appvl0 = Bool(INPUT) val pfq = Bool(INPUT) val wen = Bool(OUTPUT) - val fn = Bits(2, OUTPUT) - val sel_vcmd = Bits(3, OUTPUT) - val sel_vimm = Bits(1, OUTPUT) - val sel_vimm2 = Bits(1, OUTPUT) + val fn = Bits(OUTPUT, 2) + val sel_vcmd = Bits(OUTPUT, 3) + val sel_vimm = Bits(OUTPUT, 1) + val sel_vimm2 = Bits(OUTPUT, 1) } class ioCtrlVecInterface extends Bundle @@ -43,7 +43,7 @@ class ioCtrlVecInterface extends Bundle val vfence_ready = Bool(INPUT) val irq = Bool(INPUT) - val irq_cause = UFix(5, INPUT) + val irq_cause = UFix(INPUT, 5) val exception = Bool(OUTPUT) @@ -64,7 +64,7 @@ class ioCtrlVec extends Bundle val replay = Bool(OUTPUT) val vfence_ready = Bool(OUTPUT) val irq = Bool(OUTPUT) - val irq_cause = UFix(5, OUTPUT) + val irq_cause = UFix(OUTPUT, 5) } class rocketCtrlVecSigs extends Bundle @@ -95,7 +95,7 @@ class rocketCtrlVecDecoder extends Component { val io = new Bundle { - val inst = Bits(32, INPUT) + val inst = Bits(INPUT, 32) val sigs = new rocketCtrlVecSigs().asOutput } diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 79e00bae..df1830c3 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -9,8 +9,8 @@ import hwacha._ class ioDpathImem extends Bundle() { - val req_addr = UFix(VADDR_BITS+1, OUTPUT); - val resp_data = Bits(32, INPUT); + val req_addr = UFix(OUTPUT, VADDR_BITS+1); + val resp_data = Bits(INPUT, 32); } class ioDpathAll extends Bundle() @@ -21,12 +21,12 @@ class ioDpathAll extends Bundle() val dtlb = new ioDTLB_CPU_req_bundle().asOutput() val imem = new ioDpathImem(); val ptbr_wen = Bool(OUTPUT); - val ptbr = UFix(PADDR_BITS, OUTPUT); + val ptbr = UFix(OUTPUT, PADDR_BITS); val fpu = new ioDpathFPU(); val vec_ctrl = new ioCtrlDpathVec().flip val vec_iface = new ioDpathVecInterface() val vec_imul_req = new io_imul_req - val vec_imul_resp = Bits(hwacha.Constants.SZ_XLEN, INPUT) + val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN) } class rocketDpath extends Component diff --git a/rocket/src/main/scala/dpath_alu.scala b/rocket/src/main/scala/dpath_alu.scala index 4a0bb607..25fc2956 100644 --- a/rocket/src/main/scala/dpath_alu.scala +++ b/rocket/src/main/scala/dpath_alu.scala @@ -7,12 +7,12 @@ import Constants._ import Instructions._ class ioALU extends Bundle(){ - val dw = UFix(1, INPUT); - val fn = UFix(4, INPUT); - val in2 = UFix(64, INPUT); - val in1 = UFix(64, INPUT); - val out = UFix(64, OUTPUT); - val adder_out = UFix(64, OUTPUT); + val dw = UFix(INPUT, 1); + val fn = UFix(INPUT, 4); + val in2 = UFix(INPUT, 64); + val in1 = UFix(INPUT, 64); + val out = UFix(OUTPUT, 64); + val adder_out = UFix(OUTPUT, 64); } class rocketDpathALU extends Component diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index d93149fa..ac1a0b55 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -7,14 +7,14 @@ import scala.math._; class ioDpathBTB extends Bundle() { - val current_pc = UFix(VADDR_BITS, INPUT); + val current_pc = UFix(INPUT, VADDR_BITS); val hit = Bool(OUTPUT); - val target = UFix(VADDR_BITS, OUTPUT); + val target = UFix(OUTPUT, VADDR_BITS); val wen = Bool(INPUT); val clr = Bool(INPUT); val invalidate = Bool(INPUT); - val correct_pc = UFix(VADDR_BITS, INPUT); - val correct_target = UFix(VADDR_BITS, INPUT); + val correct_pc = UFix(INPUT, VADDR_BITS); + val correct_target = UFix(INPUT, VADDR_BITS); } // fully-associative branch target buffer @@ -63,26 +63,26 @@ class ioDpathPCR extends Bundle() val r = new ioReadPort(); val w = new ioWritePort(); - val status = Bits(32, OUTPUT); - val ptbr = UFix(PADDR_BITS, OUTPUT); - val evec = UFix(VADDR_BITS, OUTPUT); + val status = Bits(OUTPUT, 32); + val ptbr = UFix(OUTPUT, PADDR_BITS); + val evec = UFix(OUTPUT, VADDR_BITS); val exception = Bool(INPUT); - val cause = UFix(6, INPUT); + val cause = UFix(INPUT, 6); val badvaddr_wen = Bool(INPUT); - val vec_irq_aux = Bits(64, INPUT) + val vec_irq_aux = Bits(INPUT, 64) val vec_irq_aux_wen = Bool(INPUT) - val pc = UFix(VADDR_BITS+1, INPUT); + val pc = UFix(INPUT, VADDR_BITS+1); val eret = Bool(INPUT); val ei = Bool(INPUT); val di = Bool(INPUT); val ptbr_wen = Bool(OUTPUT); val irq_timer = Bool(OUTPUT); val irq_ipi = Bool(OUTPUT); - val vecbank = Bits(8, OUTPUT) - val vecbankcnt = UFix(4, OUTPUT) - val vec_appvl = UFix(12, INPUT) - val vec_nxregs = UFix(6, INPUT) - val vec_nfregs = UFix(6, INPUT) + val vecbank = Bits(OUTPUT, 8) + val vecbankcnt = UFix(OUTPUT, 4) + val vec_appvl = UFix(INPUT, 12) + val vec_nxregs = UFix(INPUT, 6) + val vec_nfregs = UFix(INPUT, 6) } class rocketDpathPCR extends Component @@ -228,16 +228,16 @@ class rocketDpathPCR extends Component class ioReadPort extends Bundle() { - val addr = UFix(5, INPUT); + val addr = UFix(INPUT, 5); val en = Bool(INPUT); - val data = Bits(64, OUTPUT); + val data = Bits(OUTPUT, 64); } class ioWritePort extends Bundle() { - val addr = UFix(5, INPUT); + val addr = UFix(INPUT, 5); val en = Bool(INPUT); - val data = Bits(64, INPUT); + val data = Bits(INPUT, 64); } class ioRegfile extends Bundle() diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala index 3c2c60c7..6f5f228f 100644 --- a/rocket/src/main/scala/dpath_vec.scala +++ b/rocket/src/main/scala/dpath_vec.scala @@ -8,13 +8,13 @@ import hwacha.Constants._ class ioDpathVecInterface extends Bundle { - val vcmdq_bits = Bits(SZ_VCMD, OUTPUT) - val vximm1q_bits = Bits(SZ_VIMM, OUTPUT) - val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT) - val vcntq_bits = Bits(SZ_VLEN, OUTPUT) + val vcmdq_bits = Bits(OUTPUT, SZ_VCMD) + val vximm1q_bits = Bits(OUTPUT, SZ_VIMM) + val vximm2q_bits = Bits(OUTPUT, SZ_VSTRIDE) + val vcntq_bits = Bits(OUTPUT, SZ_VLEN) val vcntq_last = Bool(OUTPUT) - val evac_addr = Bits(64, OUTPUT) - val irq_aux = Bits(64, INPUT) + val evac_addr = Bits(OUTPUT, 64) + val irq_aux = Bits(INPUT, 64) } class ioDpathVec extends Bundle @@ -22,18 +22,18 @@ class ioDpathVec extends Bundle val ctrl = new ioCtrlDpathVec().flip val iface = new ioDpathVecInterface() val valid = Bool(INPUT) - val inst = Bits(32, INPUT) - val waddr = UFix(5, INPUT) - val raddr1 = UFix(5, INPUT) - val vecbank = Bits(8, INPUT) - val vecbankcnt = UFix(4, INPUT) - val wdata = Bits(64, INPUT) - val rs2 = Bits(64, INPUT) + val inst = Bits(INPUT, 32) + val waddr = UFix(INPUT, 5) + val raddr1 = UFix(INPUT, 5) + val vecbank = Bits(INPUT, 8) + val vecbankcnt = UFix(INPUT, 4) + val wdata = Bits(INPUT, 64) + val rs2 = Bits(INPUT, 64) val wen = Bool(OUTPUT) - val irq_aux = Bits(64, OUTPUT) - val appvl = UFix(12, OUTPUT) - val nxregs = UFix(6, OUTPUT) - val nfregs = UFix(6, OUTPUT) + val irq_aux = Bits(OUTPUT, 64) + val appvl = UFix(OUTPUT, 12) + val nxregs = UFix(OUTPUT, 6) + val nfregs = UFix(OUTPUT, 6) } class rocketDpathVec extends Component diff --git a/rocket/src/main/scala/dtlb.scala b/rocket/src/main/scala/dtlb.scala index 7d1b6b18..99018351 100644 --- a/rocket/src/main/scala/dtlb.scala +++ b/rocket/src/main/scala/dtlb.scala @@ -23,7 +23,7 @@ class ioDTLB_CPU_resp extends Bundle { // lookup responses val miss = Bool(OUTPUT) - val ppn = Bits(PPN_BITS, OUTPUT) + val ppn = Bits(OUTPUT, PPN_BITS) val xcpt_ld = Bool(OUTPUT) val xcpt_st = Bool(OUTPUT) val xcpt_pf = Bool(OUTPUT) @@ -32,7 +32,7 @@ class ioDTLB_CPU_resp extends Bundle class ioDTLB extends Bundle { // status bits (from PCR), to check current permission and whether VM is enabled - val status = Bits(32, INPUT) + val status = Bits(INPUT, 32) // invalidate all TLB entries val invalidate = Bool(INPUT) val cpu_req = new ioDTLB_CPU_req().flip diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index d0a249bc..9f70d637 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -67,7 +67,7 @@ class rocketFPUCtrlSigs extends Bundle class rocketFPUDecoder extends Component { val io = new Bundle { - val inst = Bits(32, INPUT) + val inst = Bits(INPUT, 32) val sigs = new rocketFPUCtrlSigs().asOutput } @@ -154,16 +154,16 @@ class rocketFPUDecoder extends Component } class ioDpathFPU extends Bundle { - val inst = Bits(32, OUTPUT) - val fromint_data = Bits(64, OUTPUT) + val inst = Bits(OUTPUT, 32) + val fromint_data = Bits(OUTPUT, 64) - val store_data = Bits(64, INPUT) - val toint_data = Bits(64, INPUT) + val store_data = Bits(INPUT, 64) + val toint_data = Bits(INPUT, 64) val dmem_resp_val = Bool(OUTPUT) - val dmem_resp_type = Bits(3, OUTPUT) - val dmem_resp_tag = UFix(5, OUTPUT) - val dmem_resp_data = Bits(64, OUTPUT) + val dmem_resp_type = Bits(OUTPUT, 3) + val dmem_resp_tag = UFix(OUTPUT, 5) + val dmem_resp_data = Bits(OUTPUT, 64) } class ioCtrlFPU extends Bundle { @@ -174,23 +174,23 @@ class ioCtrlFPU extends Bundle { val killm = Bool(OUTPUT) val dec = new rocketFPUCtrlSigs().asInput val sboard_clr = Bool(INPUT) - val sboard_clra = UFix(5, INPUT) + val sboard_clra = UFix(INPUT, 5) } class rocketFPIntUnit extends Component { val io = new Bundle { val single = Bool(INPUT) - val cmd = Bits(FCMD_WIDTH, INPUT) - val rm = Bits(3, INPUT) - val fsr = Bits(FSR_WIDTH, INPUT) - val in1 = Bits(65, INPUT) - val in2 = Bits(65, INPUT) + val cmd = Bits(INPUT, FCMD_WIDTH) + val rm = Bits(INPUT, 3) + val fsr = Bits(INPUT, FSR_WIDTH) + val in1 = Bits(INPUT, 65) + val in2 = Bits(INPUT, 65) val lt_s = Bool(OUTPUT) val lt_d = Bool(OUTPUT) - val store_data = Bits(64, OUTPUT) - val toint_data = Bits(64, OUTPUT) - val exc = Bits(5, OUTPUT) + val store_data = Bits(OUTPUT, 64) + val toint_data = Bits(OUTPUT, 64) + val exc = Bits(OUTPUT, 5) } val unrec_s = hardfloat.recodedFloatNToFloatN(io.in1, 23, 9) @@ -253,17 +253,17 @@ class rocketFPUFastPipe extends Component { val io = new Bundle { val single = Bool(INPUT) - val cmd = Bits(FCMD_WIDTH, INPUT) - val rm = Bits(3, INPUT) - val fromint = Bits(64, INPUT) - val in1 = Bits(65, INPUT) - val in2 = Bits(65, INPUT) + val cmd = Bits(INPUT, FCMD_WIDTH) + val rm = Bits(INPUT, 3) + val fromint = Bits(INPUT, 64) + val in1 = Bits(INPUT, 65) + val in2 = Bits(INPUT, 65) val lt_s = Bool(INPUT) val lt_d = Bool(INPUT) - val out_s = Bits(33, OUTPUT) - val exc_s = Bits(5, OUTPUT) - val out_d = Bits(65, OUTPUT) - val exc_d = Bits(5, OUTPUT) + val out_s = Bits(OUTPUT, 33) + val exc_s = Bits(OUTPUT, 5) + val out_d = Bits(OUTPUT, 65) + val exc_d = Bits(OUTPUT, 5) } val i2s = hardfloat.anyToRecodedFloatN(io.fromint, io.rm, ~io.cmd(1,0), 23, 9, 64) @@ -339,13 +339,13 @@ class rocketFPUFastPipe extends Component class ioFMA(width: Int) extends Bundle { val valid = Bool(INPUT) - val cmd = Bits(FCMD_WIDTH, INPUT) - val rm = Bits(3, INPUT) - val in1 = Bits(width, INPUT) - val in2 = Bits(width, INPUT) - val in3 = Bits(width, INPUT) - val out = Bits(width, OUTPUT) - val exc = Bits(5, OUTPUT) + val cmd = Bits(INPUT, FCMD_WIDTH) + val rm = Bits(INPUT, 3) + val in1 = Bits(INPUT, width) + val in2 = Bits(INPUT, width) + val in3 = Bits(INPUT, width) + val out = Bits(OUTPUT, width) + val exc = Bits(OUTPUT, 5) } class rocketFPUSFMAPipe(latency: Int) extends Component diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 5318ce7a..fec70226 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -11,9 +11,9 @@ class ioImem extends Bundle val invalidate = Bool(INPUT); val itlb_miss = Bool(INPUT); val req_val = Bool(INPUT); - val req_idx = Bits(PGIDX_BITS, INPUT); - val req_ppn = Bits(PPN_BITS, INPUT); - val resp_data = Bits(32, OUTPUT); + val req_idx = Bits(INPUT, PGIDX_BITS); + val req_ppn = Bits(INPUT, PPN_BITS); + val resp_data = Bits(OUTPUT, 32); val resp_val = Bool(OUTPUT); } diff --git a/rocket/src/main/scala/itlb.scala b/rocket/src/main/scala/itlb.scala index d11fc359..dac04fa2 100644 --- a/rocket/src/main/scala/itlb.scala +++ b/rocket/src/main/scala/itlb.scala @@ -8,14 +8,14 @@ import scala.math._; class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle { val clear = Bool(INPUT); val clear_hit = Bool(INPUT) - val tag = Bits(tag_bits, INPUT); + val tag = Bits(INPUT, tag_bits); val hit = Bool(OUTPUT); - val hit_addr = UFix(addr_bits, OUTPUT); - val valid_bits = Bits(entries, OUTPUT); + val hit_addr = UFix(OUTPUT, addr_bits); + val valid_bits = Bits(OUTPUT, entries); val write = Bool(INPUT); - val write_tag = Bits(tag_bits, INPUT); - val write_addr = UFix(addr_bits, INPUT); + val write_tag = Bits(INPUT, tag_bits); + val write_addr = UFix(INPUT, addr_bits); } class rocketCAM(entries: Int, tag_bits: Int) extends Component { @@ -78,30 +78,30 @@ class ioTLB_PTW extends Bundle // requests val req_val = Bool(OUTPUT); val req_rdy = Bool(INPUT); - val req_vpn = Bits(VPN_BITS, OUTPUT); + val req_vpn = Bits(OUTPUT, VPN_BITS); // responses val resp_val = Bool(INPUT); val resp_err = Bool(INPUT); - val resp_ppn = Bits(PPN_BITS, INPUT); - val resp_perm = Bits(PERM_BITS, INPUT); + val resp_ppn = Bits(INPUT, PPN_BITS); + val resp_perm = Bits(INPUT, PERM_BITS); } // interface between ITLB and fetch stage of pipeline class ioITLB_CPU extends Bundle { // status bits (from PCR), to check current permission and whether VM is enabled - val status = Bits(32, INPUT); + val status = Bits(INPUT, 32); // invalidate all TLB entries val invalidate = Bool(INPUT); // lookup requests val req_val = Bool(INPUT); val req_rdy = Bool(OUTPUT); - val req_asid = Bits(ASID_BITS, INPUT); - val req_vpn = UFix(VPN_BITS+1, INPUT); + val req_asid = Bits(INPUT, ASID_BITS); + val req_vpn = UFix(INPUT, VPN_BITS+1); // lookup responses val resp_miss = Bool(OUTPUT); // val resp_val = Bool(OUTPUT); - val resp_ppn = UFix(PPN_BITS, OUTPUT); + val resp_ppn = UFix(OUTPUT, PPN_BITS); val exception = Bool(OUTPUT); } diff --git a/rocket/src/main/scala/llc.scala b/rocket/src/main/scala/llc.scala index e6f39c4a..5f5007d1 100644 --- a/rocket/src/main/scala/llc.scala +++ b/rocket/src/main/scala/llc.scala @@ -7,7 +7,7 @@ import Constants._ class BigMem[T <: Data](n: Int, readLatency: Int, leaf: Mem[Bits])(gen: => T) extends Component { val io = new Bundle { - val addr = UFix(log2Up(n), INPUT) + val addr = UFix(INPUT, log2Up(n)) val en = Bool(INPUT) val rw = Bool(INPUT) val wdata = gen.asInput @@ -99,17 +99,17 @@ class LLCMSHRFile(sets: Int, ways: Int, outstanding: Int) extends Component { val io = new Bundle { val cpu = (new FIFOIO) { new MemReqCmd }.flip - val repl_way = UFix(log2Up(ways), INPUT) + val repl_way = UFix(INPUT, log2Up(ways)) val repl_dirty = Bool(INPUT) - val repl_tag = UFix(PADDR_BITS - OFFSET_BITS - log2Up(sets), INPUT) + val repl_tag = UFix(INPUT, PADDR_BITS - OFFSET_BITS - log2Up(sets)) val data = (new FIFOIO) { new LLCDataReq(ways) } val tag = (new FIFOIO) { new Bundle { val addr = UFix(width = PADDR_BITS - OFFSET_BITS) val way = UFix(width = log2Up(ways)) } } val mem = new ioMem - val mem_resp_set = UFix(log2Up(sets), OUTPUT) - val mem_resp_way = UFix(log2Up(ways), OUTPUT) + val mem_resp_set = UFix(OUTPUT, log2Up(sets)) + val mem_resp_way = UFix(OUTPUT, log2Up(ways)) } class MSHR extends Bundle { @@ -247,8 +247,8 @@ class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component val writeback_data = (new FIFOIO) { new MemData } val resp = (new PipeIO) { new MemResp } val mem_resp = (new PipeIO) { new MemResp }.flip - val mem_resp_set = UFix(log2Up(sets), INPUT) - val mem_resp_way = UFix(log2Up(ways), INPUT) + val mem_resp_set = UFix(INPUT, log2Up(sets)) + val mem_resp_way = UFix(INPUT, log2Up(ways)) } val data = new BigMem(sets*ways*REFILL_CYCLES, 2, leaf)(Bits(width = MEM_DATA_BITS)) diff --git a/rocket/src/main/scala/multiplier.scala b/rocket/src/main/scala/multiplier.scala index a0e69332..9d3145b5 100644 --- a/rocket/src/main/scala/multiplier.scala +++ b/rocket/src/main/scala/multiplier.scala @@ -8,12 +8,12 @@ import hwacha.Constants._ class ioMultiplier extends Bundle { val req = new io_imul_req().flip - val req_tag = Bits(5, INPUT) + val req_tag = Bits(INPUT, 5) val req_kill = Bool(INPUT) val resp_val = Bool(OUTPUT) val resp_rdy = Bool(INPUT) - val resp_tag = Bits(5, OUTPUT) - val resp_bits = Bits(SZ_XLEN, OUTPUT) + val resp_tag = Bits(OUTPUT, 5) + val resp_bits = Bits(OUTPUT, SZ_XLEN) } class rocketVUMultiplier(nwbq: Int) extends Component { @@ -21,7 +21,7 @@ class rocketVUMultiplier(nwbq: Int) extends Component { val cpu = new ioMultiplier val vu = new Bundle { val req = new io_imul_req - val resp = Bits(SZ_XLEN, INPUT) + val resp = Bits(INPUT, SZ_XLEN) } } diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index fdc7376a..c99cc0e0 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -22,9 +22,9 @@ class RandomReplacementWayGen extends Component { class StoreMaskGen extends Component { val io = new Bundle { - val typ = Bits(3, INPUT) - val addr = Bits(3, INPUT) - val wmask = Bits(8, OUTPUT) + val typ = Bits(INPUT, 3) + val addr = Bits(INPUT, 3) + val wmask = Bits(OUTPUT, 8) } val word = (io.typ === MT_W) || (io.typ === MT_WU) @@ -39,9 +39,9 @@ class StoreMaskGen extends Component { class StoreDataGen extends Component { val io = new Bundle { - val typ = Bits(3, INPUT) - val din = Bits(64, INPUT) - val dout = Bits(64, OUTPUT) + val typ = Bits(INPUT, 3) + val din = Bits(INPUT, 64) + val dout = Bits(OUTPUT, 64) } val word = (io.typ === MT_W) || (io.typ === MT_WU) @@ -57,12 +57,12 @@ class StoreDataGen extends Component { // this currently requires that CPU_DATA_BITS == 64 class LoadDataGen extends Component { val io = new Bundle { - val typ = Bits(3, INPUT) - val addr = Bits(log2Up(MEM_DATA_BITS/8), INPUT) - val din = Bits(MEM_DATA_BITS, INPUT) - val dout = Bits(64, OUTPUT) - val r_dout = Bits(64, OUTPUT) - val r_dout_subword = Bits(64, OUTPUT) + val typ = Bits(INPUT, 3) + val addr = Bits(INPUT, log2Up(MEM_DATA_BITS/8)) + val din = Bits(INPUT, MEM_DATA_BITS) + val dout = Bits(OUTPUT, 64) + val r_dout = Bits(OUTPUT, 64) + val r_dout_subword = Bits(OUTPUT, 64) } val sext = (io.typ === MT_B) || (io.typ === MT_H) || @@ -165,13 +165,13 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component { val req_sec_val = Bool(INPUT) val req_sec_rdy = Bool(OUTPUT) val req_bits = new MSHRReq().asInput - val req_sdq_id = UFix(log2Up(NSDQ), INPUT) + val req_sdq_id = UFix(INPUT, log2Up(NSDQ)) val idx_match = Bool(OUTPUT) - val idx = Bits(IDX_BITS, OUTPUT) - val refill_count = Bits(log2Up(REFILL_CYCLES), OUTPUT) - val tag = Bits(TAG_BITS, OUTPUT) - val way_oh = Bits(NWAYS, OUTPUT) + val idx = Bits(OUTPUT, IDX_BITS) + val refill_count = Bits(OUTPUT, log2Up(REFILL_CYCLES)) + val tag = Bits(OUTPUT, TAG_BITS) + val way_oh = Bits(OUTPUT, NWAYS) val mem_req = (new FIFOIO) { new TransactionInit } val meta_req = (new FIFOIO) { new MetaArrayReq() } @@ -297,9 +297,9 @@ class MSHRFile(co: CoherencePolicy) extends Component { val req = (new FIFOIO) { new MSHRReq }.flip val secondary_miss = Bool(OUTPUT) - val mem_resp_idx = Bits(IDX_BITS, OUTPUT) - val mem_resp_offset = Bits(log2Up(REFILL_CYCLES), OUTPUT) - val mem_resp_way_oh = Bits(NWAYS, OUTPUT) + val mem_resp_idx = Bits(OUTPUT, IDX_BITS) + val mem_resp_offset = Bits(OUTPUT, log2Up(REFILL_CYCLES)) + val mem_resp_way_oh = Bits(OUTPUT, NWAYS) val fence_rdy = Bool(OUTPUT) @@ -313,7 +313,7 @@ class MSHRFile(co: CoherencePolicy) extends Component { val probe = (new FIFOIO) { Bool() }.flip val cpu_resp_val = Bool(OUTPUT) - val cpu_resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT) + val cpu_resp_tag = Bits(OUTPUT, DCACHE_TAG_BITS) } val sdq_val = Reg(resetVal = Bits(0, NSDQ)) @@ -419,7 +419,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component { val req = (new FIFOIO) { new WritebackReq() }.flip val probe = (new FIFOIO) { new WritebackReq() }.flip val data_req = (new FIFOIO) { new DataArrayReq() } - val data_resp = Bits(MEM_DATA_BITS, INPUT) + val data_resp = Bits(INPUT, MEM_DATA_BITS) val mem_req = (new FIFOIO) { new TransactionInit } val mem_req_data = (new FIFOIO) { new TransactionInitData } val probe_rep_data = (new FIFOIO) { new ProbeReplyData } @@ -490,9 +490,9 @@ class ProbeUnit(co: CoherencePolicy) extends Component { val meta_req = (new FIFOIO) { new MetaArrayReq } val mshr_req = (new FIFOIO) { Bool() } val wb_req = (new FIFOIO) { new WritebackReq } - val tag_match_way_oh = Bits(NWAYS, INPUT) - val line_state = UFix(2, INPUT) - val address = Bits(PADDR_BITS-OFFSET_BITS, OUTPUT) + val tag_match_way_oh = Bits(INPUT, NWAYS) + val line_state = UFix(INPUT, 2) + val address = Bits(OUTPUT, PADDR_BITS-OFFSET_BITS) } val s_invalid :: s_meta_req :: s_meta_resp :: s_mshr_req :: s_probe_rep :: s_writeback_req :: s_writeback_resp :: Nil = Enum(7) { UFix() } @@ -659,7 +659,7 @@ class DataArray(lines: Int) extends Component { class DataArrayArray(lines: Int) extends Component { val io = new Bundle { val req = (new FIFOIO) { new DataArrayReq() }.flip - val resp = Vec(NWAYS){ Bits(width = MEM_DATA_BITS, dir = OUTPUT) } + val resp = Vec(NWAYS){ Bits(dir = OUTPUT, width = MEM_DATA_BITS) } val way_en = Bits(width = NWAYS, dir = OUTPUT) } @@ -681,11 +681,11 @@ class DataArrayArray(lines: Int) extends Component { class AMOALU extends Component { val io = new Bundle { - val cmd = Bits(4, INPUT) - val typ = Bits(3, INPUT) - val lhs = UFix(64, INPUT) - val rhs = UFix(64, INPUT) - val out = UFix(64, OUTPUT) + val cmd = Bits(INPUT, 4) + val typ = Bits(INPUT, 3) + val lhs = UFix(INPUT, 64) + val rhs = UFix(INPUT, 64) + val out = UFix(OUTPUT, 64) } val sgned = (io.cmd === M_XA_MIN) || (io.cmd === M_XA_MAX) diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index f1d05e06..d0c540c5 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -75,7 +75,7 @@ class ioPTW(n: Int) extends Bundle { val requestor = Vec(n) { new ioTLB_PTW }.flip val mem = new ioHellaCache - val ptbr = UFix(PADDR_BITS, INPUT) + val ptbr = UFix(INPUT, PADDR_BITS) } class rocketPTW(n: Int) extends Component diff --git a/rocket/src/main/scala/queues.scala b/rocket/src/main/scala/queues.scala index d78df502..752f986b 100644 --- a/rocket/src/main/scala/queues.scala +++ b/rocket/src/main/scala/queues.scala @@ -8,7 +8,7 @@ class ioQueue[T <: Data](entries: Int, flushable: Boolean)(data: => T) extends B val flush = if (flushable) Bool(INPUT) else null val enq = new FIFOIO()(data).flip val deq = new FIFOIO()(data) - val count = UFix(log2Up(entries+1), OUTPUT) + val count = UFix(OUTPUT, log2Up(entries+1)) } class queue[T <: Data](val entries: Int, pipe: Boolean = false, flushable: Boolean = false)(data: => T) extends Component diff --git a/rocket/src/main/scala/uncore.scala b/rocket/src/main/scala/uncore.scala index 6239981f..7e34492c 100644 --- a/rocket/src/main/scala/uncore.scala +++ b/rocket/src/main/scala/uncore.scala @@ -56,8 +56,8 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component { val p_data = (new PipeIO) { new TrackerProbeData }.flip val can_alloc = Bool(INPUT) val xact_finish = Bool(INPUT) - val p_rep_cnt_dec = Bits(ntiles, INPUT) - val p_req_cnt_inc = Bits(ntiles, INPUT) + val p_rep_cnt_dec = Bits(INPUT, ntiles) + val p_req_cnt_inc = Bits(INPUT, ntiles) val p_rep_data = (new PipeIO) { new ProbeReplyData }.flip val x_init_data = (new PipeIO) { new TransactionInitData }.flip val sent_x_rep_ack = Bool(INPUT) @@ -69,19 +69,19 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component { val mem_req_lock = Bool(OUTPUT) val probe_req = (new FIFOIO) { new ProbeRequest } val busy = Bool(OUTPUT) - val addr = Bits(PADDR_BITS - OFFSET_BITS, OUTPUT) - val init_tile_id = Bits(TILE_ID_BITS, OUTPUT) - val p_rep_tile_id = Bits(TILE_ID_BITS, OUTPUT) - val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT) - val sharer_count = Bits(TILE_ID_BITS+1, OUTPUT) - val x_type = Bits(X_INIT_TYPE_MAX_BITS, OUTPUT) - val push_p_req = Bits(ntiles, OUTPUT) - val pop_p_rep = Bits(ntiles, OUTPUT) - val pop_p_rep_data = Bits(ntiles, OUTPUT) - val pop_p_rep_dep = Bits(ntiles, OUTPUT) - val pop_x_init = Bits(ntiles, OUTPUT) - val pop_x_init_data = Bits(ntiles, OUTPUT) - val pop_x_init_dep = Bits(ntiles, OUTPUT) + val addr = Bits(OUTPUT, PADDR_BITS - OFFSET_BITS) + val init_tile_id = Bits(OUTPUT, TILE_ID_BITS) + val p_rep_tile_id = Bits(OUTPUT, TILE_ID_BITS) + val tile_xact_id = Bits(OUTPUT, TILE_XACT_ID_BITS) + val sharer_count = Bits(OUTPUT, TILE_ID_BITS+1) + val x_type = Bits(OUTPUT, X_INIT_TYPE_MAX_BITS) + val push_p_req = Bits(OUTPUT, ntiles) + val pop_p_rep = Bits(OUTPUT, ntiles) + val pop_p_rep_data = Bits(OUTPUT, ntiles) + val pop_p_rep_dep = Bits(OUTPUT, ntiles) + val pop_x_init = Bits(OUTPUT, ntiles) + val pop_x_init_data = Bits(OUTPUT, ntiles) + val pop_x_init_dep = Bits(OUTPUT, ntiles) val send_x_rep_ack = Bool(OUTPUT) }