riscv/rocket-chip
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INPUT/OUTPUT orderring swapped

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This commit is contained in:
Huy Vo
2012-07-12 18:12:49 -07:00
parent bac82762d3
commit fd95159837
17 changed files with 182 additions and 182 deletions
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6
rocket/src/main/scala/icache.scala
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@ -11,9 +11,9 @@ class ioImem extends Bundle
val invalidate = Bool(INPUT);
val itlb_miss = Bool(INPUT);
val req_val = Bool(INPUT);
val req_idx = Bits(PGIDX_BITS, INPUT);
val req_ppn = Bits(PPN_BITS, INPUT);
val resp_data = Bits(32, OUTPUT);
val req_idx = Bits(INPUT, PGIDX_BITS);
val req_ppn = Bits(INPUT, PPN_BITS);
val resp_data = Bits(OUTPUT, 32);
val resp_val = Bool(OUTPUT);
}