jtag: make it easier to assign MFR ID externally

src/main/scala/rocketchip/DebugTransport.scala

@@ -64,6 +64,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
     val dmi = new DMIIO()(p)
     val jtag = Flipped(new JTAGIO(hasTRSTn = false))
     val jtag_reset = Bool(INPUT)
+    val jtag_mfr_id = UInt(INPUT, 11)
     val fsmReset = Bool(OUTPUT)
   }
 
@@ -210,12 +211,19 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
 
   //--------------------------------------------------------
   // Actual JTAG TAP
+  val idcode = Wire(init = new JTAGIdcodeBundle().fromBits(0.U))
+  idcode.always1    := 1.U
+  idcode.version    := c.idcodeVersion.U
+  idcode.partNumber := c.idcodePartNum.U
+  idcode.mfrId      := io.jtag_mfr_id
 
   val tapIO = JtagTapGenerator(irLength = 5,
     instructions = Map(dtmJTAGAddrs.DMI_ACCESS -> dmiAccessChain,
       dtmJTAGAddrs.DTM_INFO   -> dtmInfoChain),
-    idcode = Some((dtmJTAGAddrs.IDCODE, JtagIdcode(c.idcodeVersion, c.idcodePartNum, c.idcodeManufId))))
+    icode = Some(dtmJTAGAddrs.IDCODE)
+  )
 
+  tapIO.idcode.get := idcode
   tapIO.jtag <> io.jtag
 
   tapIO.control.jtag_reset := io.jtag_reset

src/main/scala/rocketchip/RISCVPlatform.scala

@@ -24,6 +24,7 @@ trait PeripheryJTAGDTMBundle extends HasTopLevelNetworksBundle {
 
   val jtag = new JTAGIO(hasTRSTn = false).flip
   val jtag_reset = Bool(INPUT)
+  val jtag_mfr_id = UInt(INPUT, 11)
 
 }
 
@@ -36,6 +37,7 @@ trait PeripheryJTAGDTMModule extends HasTopLevelNetworksModule {
   
   dtm.clock             := io.jtag.TCK
   dtm.io.jtag_reset     := io.jtag_reset
+  dtm.io.jtag_mfr_id    := io.jtag_mfr_id
   dtm.reset             := dtm.io.fsmReset
 
   outer.coreplex.module.io.debug.dmi <> dtm.io.dmi
@@ -79,6 +81,7 @@ trait PeripheryDebugBundle extends HasTopLevelNetworksBundle {
 
   val jtag        = (p(IncludeJtagDTM)).option(new JTAGIO(hasTRSTn = false).flip)
   val jtag_reset  = (p(IncludeJtagDTM)).option(Bool(INPUT))
+  val jtag_mfr_id = (p(IncludeJtagDTM)).option(UInt(INPUT, 11))
 
   val ndreset = Bool(OUTPUT)
   val dmactive = Bool(OUTPUT)
@@ -96,6 +99,7 @@ trait PeripheryDebugModule extends HasTopLevelNetworksModule {
 
     dtm.clock          := io.jtag.get.TCK
     dtm.io.jtag_reset  := io.jtag_reset.get
+    dtm.io.jtag_mfr_id := io.jtag_mfr_id.get
     dtm.reset          := dtm.io.fsmReset
 
     outer.coreplex.module.io.debug.dmi <> dtm.io.dmi

src/main/scala/rocketchip/TestHarness.scala

@@ -28,6 +28,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
     val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug.get, io.success)
   } else {
     val jtag = Module(new JTAGVPI).connect(dut.io.jtag.get, dut.io.jtag_reset.get, reset, io.success)
+    dut.io.jtag_mfr_id.get := p(JtagDTMKey).idcodeManufId.U(11.W)
   }
 
   val mmio_sim = Module(LazyModule(new SimAXIMem(1, 4096)).module)