riscv/rocket-chip
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support non-power-of-2 queue sizes

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need to manually wrap queue pointers.
This commit is contained in:
Andrew Waterman 2012-03-13 01:56:10 -07:00
parent cbf7b13341
commit fd29e00db0
1 changed files with 3 additions and 2 deletions
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5
rocket/src/main/scala/queues.scala
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@ -24,12 +24,13 @@ class queue[T <: Data](entries: Int, pipe: Boolean = false, flushable: Boolean =
{ {
enq_ptr = Reg(resetVal = UFix(0, log2up(entries))) enq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
deq_ptr = Reg(resetVal = UFix(0, log2up(entries))) deq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
val pow2 = Bool((entries & (entries-1)) == 0)
when (do_deq) { when (do_deq) {
deq_ptr := deq_ptr + UFix(1) deq_ptr := Mux(!pow2 && deq_ptr === UFix(entries-1), UFix(0), deq_ptr + UFix(1))
} }
when (do_enq) { when (do_enq) {
enq_ptr := enq_ptr + UFix(1) enq_ptr := Mux(!pow2 && enq_ptr === UFix(entries-1), UFix(0), enq_ptr + UFix(1))
} }
if (flushable) { if (flushable) {
when (io.flush) { when (io.flush) {