riscv/rocket-chip
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fix connection error in fpga uncore

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Henry Cook
2014-04-24 11:58:59 -07:00
parent 1e062d1bcd
commit fbf6e44376
1 changed files with 1 additions and 1 deletions
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src/main/scala/fpga.scala
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@@ -64,7 +64,7 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo
case ((outer, client), i) => case ((outer, client), i) =>
outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _)) outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _)) outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.release, i)) outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.grant_ack, i))
client.grant <> Queue(outer.grant, 1, pipe = true) client.grant <> Queue(outer.grant, 1, pipe = true)
client.probe <> Queue(outer.probe) client.probe <> Queue(outer.probe)
} }