diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index 79203e40..6ecabdaf 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -64,7 +64,7 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo
     case ((outer, client), i) => 
       outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
       outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
-      outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.release, i))
+      outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.grant_ack, i))
       client.grant <> Queue(outer.grant, 1, pipe = true)
       client.probe <> Queue(outer.probe)
   }