update to new isa; disable vector tests
This commit is contained in:
Andrew Waterman
parent
b42e140e05
commit
fbdbb01232
22
Makefrag
22
Makefrag
@ -20,8 +20,6 @@ src_path = src/main/scala
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tstdir = $(base_dir)/riscv-tests/isa
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asm_p_tests = \
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rv64si-pm-ipi \
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rv64ui-pm-lrsc \
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rv64ui-p-add \
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rv64ui-p-addi \
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rv64ui-p-amoadd_d \
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@ -30,6 +28,8 @@ asm_p_tests = \
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rv64ui-p-amoand_w \
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rv64ui-p-amoor_d \
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rv64ui-p-amoor_w \
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rv64ui-p-amoxor_d \
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rv64ui-p-amoxor_w \
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rv64ui-p-amoswap_d \
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rv64ui-p-amoswap_w \
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rv64ui-p-amomax_d \
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@ -63,8 +63,6 @@ asm_p_tests = \
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rv64ui-p-j \
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rv64ui-p-jal \
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rv64ui-p-jalr \
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rv64ui-p-jalr_j \
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rv64ui-p-jalr_r \
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rv64ui-p-lb \
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rv64ui-p-lbu \
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rv64ui-p-ld \
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@ -113,6 +111,8 @@ asm_p_tests = \
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rv64uf-p-fmin \
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rv64uf-p-fmadd \
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rv64uf-p-structural \
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rv64si-pm-ipi \
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rv64ui-pm-lrsc \
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asm_v_tests = \
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rv64ui-v-add \
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@ -123,6 +123,8 @@ asm_v_tests = \
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rv64ui-v-amoand_w \
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rv64ui-v-amoor_d \
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rv64ui-v-amoor_w \
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rv64ui-v-amoxor_d \
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rv64ui-v-amoxor_w \
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rv64ui-v-amoswap_d \
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rv64ui-v-amoswap_w \
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rv64ui-v-amomax_d \
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@ -156,8 +158,6 @@ asm_v_tests = \
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rv64ui-v-j \
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rv64ui-v-jal \
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rv64ui-v-jalr \
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rv64ui-v-jalr_j \
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rv64ui-v-jalr_r \
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rv64ui-v-lb \
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rv64ui-v-lbu \
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rv64ui-v-ld \
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@ -503,11 +503,11 @@ bmarks = \
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dgemm.riscv \
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dhrystone.riscv \
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spmv.riscv \
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vec-vvadd.riscv \
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vec-cmplxmult.riscv \
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vec-matmul.riscv \
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mt-vvadd.riscv \
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mt-matmul.riscv \
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#vec-vvadd.riscv \
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#vec-cmplxmult.riscv \
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#vec-matmul.riscv \
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#mt-vvadd.riscv \
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#mt-matmul.riscv \
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vec_bmarkdir = $(base_dir)/../../riscv-app/misc/build
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vec_bmarks = \
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@ -125,13 +125,6 @@ int main(int argc, char** argv)
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tile.Top__io_host_out_ready = LIT<1>(1);
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}
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if (tile.Top__io_debug_error_mode.lo_word())
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{
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failure = "entered error mode";
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break;
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}
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if (log)
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tile.print(stderr);
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@ -106,6 +106,6 @@ run-bmarks-test-debug: $(addprefix output/, $(addsuffix .vpd, $(bmarks)))
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run-mt-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(mt_bmarks)))
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@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
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run: run-asm-tests run-vecasm-tests run-vecasm-timer-tests run-bmarks-test
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run-debug: run-asm-tests-debug run-vecasm-tests-debug run-vecasm-timer-tests-debug run-bmarks-test-debug
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run: run-asm-tests run-bmarks-test #run-vecasm-tests run-vecasm-timer-tests
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run-debug: run-asm-tests-debug run-bmarks-test-debug #run-vecasm-tests-debug run-vecasm-timer-tests-debug
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run-fast: $(addprefix output/, $(addsuffix .run, $(asm_p_tests) $(asm_v_tests) $(bmarks)))
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@ -1 +1 @@
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Subproject commit c31d7c5eb4109fdcce58d27b132e20596ece2d07
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Subproject commit 728924ea6db6f6c3ee11554c3ad79d9bdabbe57e
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2
rocket
2
rocket
@ -1 +1 @@
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Subproject commit b239d7f9ad8c127c3ef6f9912ad0bf5771817fe5
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Subproject commit 9b3b586bbbe38c7b455615a073716f6f6946df44
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@ -145,7 +145,6 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
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{
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implicit val tl = conf.tl
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val io = new Bundle {
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val debug = new DebugIO()
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val host = new HostIO(htif_width)
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val mem = new ioMem
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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@ -212,7 +211,6 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
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}
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class TopIO(htifWidth: Int) extends Bundle {
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val debug = new DebugIO
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val host = new HostIO(htifWidth)
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val mem = new ioMem
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}
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@ -259,7 +257,6 @@ class Top extends Module {
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val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
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val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
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var error_mode = Bool(false)
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for (i <- 0 until uc.nTiles) {
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val hl = uncore.io.htif(i)
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val tl = uncore.io.tiles(i)
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@ -270,11 +267,11 @@ class Top extends Module {
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tile.io.tilelink <> tl
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il := hl.reset
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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tile.io.host.pcr_req <> Queue(hl.pcr_req)
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hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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error_mode = error_mode || Reg(next=tile.io.host.debug.error_mode)
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tile.io.host.pcr_req <> Queue(hl.pcr_req, 1)
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tile.io.host.id := i
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hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1)
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hl.ipi_req <> Queue(tile.io.host.ipi_req, 1)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1)
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}
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io.host <> uncore.io.host
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@ -286,5 +283,4 @@ class Top extends Module {
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io.mem_backup_en <> uncore.io.mem_backup_en
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io.mem <> uncore.io.mem
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io.debug.error_mode := error_mode
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}
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@ -39,7 +39,6 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
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{
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implicit val (tl, ln) = (conf.tl, conf.tl.ln)
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val io = new Bundle {
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val debug = new DebugIO()
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val host = new HostIO(htif_width)
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val mem = new ioMem
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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@ -103,7 +102,6 @@ class FPGATop extends Module {
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val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
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val uncore = Module(new FPGAUncore(htif_width, tileList))
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io.debug.error_mode := Bool(false)
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for (i <- 0 until uc.nTiles) {
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val hl = uncore.io.htif(i)
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val tl = uncore.io.tiles(i)
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@ -114,13 +112,12 @@ class FPGATop extends Module {
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tile.io.tilelink <> tl
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il := hl.reset
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tile.io.host.id := UInt(i)
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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tile.io.host.pcr_req <> Queue(hl.pcr_req)
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hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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when (tile.io.host.debug.error_mode) { io.debug.error_mode := Bool(true) }
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}
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io.host <> uncore.io.host
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@ -144,7 +141,7 @@ class Slave extends AXISlave
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val memw = top.io.mem.resp.bits.data.getWidth
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val htifw = top.io.host.in.bits.getWidth
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val n = 4 // htif, mem req/read data, mem write data, error mode
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val n = 4
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def wen(i: Int) = io.in.valid && io.addr(log2Up(n)-1,0) === UInt(i)
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def ren(i: Int) = io.out.ready && io.addr(log2Up(n)-1,0) === UInt(i)
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val rdata = Vec.fill(n){Bits(width = dw)}
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@ -201,8 +198,8 @@ class Slave extends AXISlave
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rvalid(2) := top.io.mem.req_data.valid
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when (ren(2) && rvalid(2)) { out_count := out_count + UInt(1) }
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// read cr3 -> error mode (nonblocking)
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rdata(3) := Cat(top.io.mem.req_cmd.valid, tagq.io.enq.ready, top.io.debug.error_mode)
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// read cr3 -> debug signals (nonblocking)
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rdata(3) := Cat(top.io.mem.req_cmd.valid, tagq.io.enq.ready)
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rvalid(3) := Bool(true)
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// writes to cr2, cr3 ignored
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit 0cc26c501efad36463e3195f3b0992ed31833e73
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Subproject commit 3dd49c34aad2256865fb3500fcbf1626d3b1b01b
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