diff --git a/Makefrag b/Makefrag
index 08a545e6..b83f3c97 100644
--- a/Makefrag
+++ b/Makefrag
@@ -20,8 +20,6 @@ src_path = src/main/scala
 
 tstdir = $(base_dir)/riscv-tests/isa
 asm_p_tests = \
-	rv64si-pm-ipi \
-	rv64ui-pm-lrsc \
 	rv64ui-p-add \
 	rv64ui-p-addi \
 	rv64ui-p-amoadd_d \
@@ -30,6 +28,8 @@ asm_p_tests = \
 	rv64ui-p-amoand_w \
 	rv64ui-p-amoor_d \
 	rv64ui-p-amoor_w \
+	rv64ui-p-amoxor_d \
+	rv64ui-p-amoxor_w \
 	rv64ui-p-amoswap_d \
 	rv64ui-p-amoswap_w \
 	rv64ui-p-amomax_d \
@@ -63,8 +63,6 @@ asm_p_tests = \
 	rv64ui-p-j \
 	rv64ui-p-jal \
 	rv64ui-p-jalr \
-	rv64ui-p-jalr_j \
-	rv64ui-p-jalr_r \
 	rv64ui-p-lb \
 	rv64ui-p-lbu \
 	rv64ui-p-ld \
@@ -113,6 +111,8 @@ asm_p_tests = \
 	rv64uf-p-fmin \
 	rv64uf-p-fmadd \
 	rv64uf-p-structural \
+	rv64si-pm-ipi \
+	rv64ui-pm-lrsc \
 
 asm_v_tests = \
 	rv64ui-v-add \
@@ -123,6 +123,8 @@ asm_v_tests = \
 	rv64ui-v-amoand_w \
 	rv64ui-v-amoor_d \
 	rv64ui-v-amoor_w \
+	rv64ui-v-amoxor_d \
+	rv64ui-v-amoxor_w \
 	rv64ui-v-amoswap_d \
 	rv64ui-v-amoswap_w \
 	rv64ui-v-amomax_d \
@@ -156,8 +158,6 @@ asm_v_tests = \
 	rv64ui-v-j \
 	rv64ui-v-jal \
 	rv64ui-v-jalr \
-	rv64ui-v-jalr_j \
-	rv64ui-v-jalr_r \
 	rv64ui-v-lb \
 	rv64ui-v-lbu \
 	rv64ui-v-ld \
@@ -503,11 +503,11 @@ bmarks = \
 	dgemm.riscv \
 	dhrystone.riscv \
 	spmv.riscv \
-	vec-vvadd.riscv \
-	vec-cmplxmult.riscv \
-	vec-matmul.riscv \
-	mt-vvadd.riscv \
-	mt-matmul.riscv \
+	#vec-vvadd.riscv \
+	#vec-cmplxmult.riscv \
+	#vec-matmul.riscv \
+	#mt-vvadd.riscv \
+	#mt-matmul.riscv \
 
 vec_bmarkdir = $(base_dir)/../../riscv-app/misc/build
 vec_bmarks = \
diff --git a/csrc/emulator.cc b/csrc/emulator.cc
index d9cddacc..dc17f82a 100644
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@@ -125,13 +125,6 @@ int main(int argc, char** argv)
       tile.Top__io_host_out_ready = LIT<1>(1);
     }
 
-  
-    if (tile.Top__io_debug_error_mode.lo_word())
-    {
-      failure = "entered error mode";
-      break;
-    }
-
     if (log)
       tile.print(stderr);
 
diff --git a/emulator/Makefile b/emulator/Makefile
index 37ff5a10..cf56a609 100644
--- a/emulator/Makefile
+++ b/emulator/Makefile
@@ -106,6 +106,6 @@ run-bmarks-test-debug: $(addprefix output/, $(addsuffix .vpd, $(bmarks)))
 run-mt-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(mt_bmarks)))
 	@echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
 
-run: run-asm-tests run-vecasm-tests run-vecasm-timer-tests run-bmarks-test
-run-debug: run-asm-tests-debug run-vecasm-tests-debug run-vecasm-timer-tests-debug run-bmarks-test-debug
+run: run-asm-tests run-bmarks-test #run-vecasm-tests run-vecasm-timer-tests
+run-debug: run-asm-tests-debug run-bmarks-test-debug #run-vecasm-tests-debug run-vecasm-timer-tests-debug
 run-fast: $(addprefix output/, $(addsuffix .run, $(asm_p_tests) $(asm_v_tests) $(bmarks)))
diff --git a/riscv-tests b/riscv-tests
index c31d7c5e..728924ea 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit c31d7c5eb4109fdcce58d27b132e20596ece2d07
+Subproject commit 728924ea6db6f6c3ee11554c3ad79d9bdabbe57e
diff --git a/rocket b/rocket
index b239d7f9..9b3b586b 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit b239d7f9ad8c127c3ef6f9912ad0bf5771817fe5
+Subproject commit 9b3b586bbbe38c7b455615a073716f6f6946df44
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index ac378e8a..4c304359 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -145,7 +145,6 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
 {
   implicit val tl = conf.tl
   val io = new Bundle {
-    val debug = new DebugIO()
     val host = new HostIO(htif_width)
     val mem = new ioMem
     val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
@@ -212,7 +211,6 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
 }
 
 class TopIO(htifWidth: Int) extends Bundle  {
-  val debug   = new DebugIO
   val host    = new HostIO(htifWidth)
   val mem     = new ioMem
 }
@@ -259,7 +257,6 @@ class Top extends Module {
   val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
   val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
 
-  var error_mode = Bool(false)
   for (i <- 0 until uc.nTiles) {
     val hl = uncore.io.htif(i)
     val tl = uncore.io.tiles(i)
@@ -270,11 +267,11 @@ class Top extends Module {
     tile.io.tilelink <> tl
     il := hl.reset
     tile.io.host.reset := Reg(next=Reg(next=hl.reset))
-    tile.io.host.pcr_req <> Queue(hl.pcr_req)
-    hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
-    hl.ipi_req <> Queue(tile.io.host.ipi_req)
-    tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
-    error_mode = error_mode || Reg(next=tile.io.host.debug.error_mode)
+    tile.io.host.pcr_req <> Queue(hl.pcr_req, 1)
+    tile.io.host.id := i
+    hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1)
+    hl.ipi_req <> Queue(tile.io.host.ipi_req, 1)
+    tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1)
   }
 
   io.host <> uncore.io.host
@@ -286,5 +283,4 @@ class Top extends Module {
 
   io.mem_backup_en <> uncore.io.mem_backup_en
   io.mem <> uncore.io.mem
-  io.debug.error_mode := error_mode
 }
diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index 7569bea3..40034bf3 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -39,7 +39,6 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
 {
   implicit val (tl, ln) = (conf.tl, conf.tl.ln)
   val io = new Bundle {
-    val debug = new DebugIO()
     val host = new HostIO(htif_width)
     val mem = new ioMem
     val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
@@ -103,7 +102,6 @@ class FPGATop extends Module {
   val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
   val uncore = Module(new FPGAUncore(htif_width, tileList))
 
-  io.debug.error_mode := Bool(false)
   for (i <- 0 until uc.nTiles) {
     val hl = uncore.io.htif(i)
     val tl = uncore.io.tiles(i)
@@ -114,13 +112,12 @@ class FPGATop extends Module {
 
     tile.io.tilelink <> tl
     il := hl.reset
+    tile.io.host.id := UInt(i)
     tile.io.host.reset := Reg(next=Reg(next=hl.reset))
     tile.io.host.pcr_req <> Queue(hl.pcr_req)
     hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
     hl.ipi_req <> Queue(tile.io.host.ipi_req)
     tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
-
-    when (tile.io.host.debug.error_mode) { io.debug.error_mode := Bool(true) }
   }
 
   io.host <> uncore.io.host
@@ -144,7 +141,7 @@ class Slave extends AXISlave
   val memw = top.io.mem.resp.bits.data.getWidth
   val htifw = top.io.host.in.bits.getWidth
   
-  val n = 4 // htif, mem req/read data, mem write data, error mode
+  val n = 4
   def wen(i: Int) = io.in.valid && io.addr(log2Up(n)-1,0) === UInt(i)
   def ren(i: Int) = io.out.ready && io.addr(log2Up(n)-1,0) === UInt(i)
   val rdata = Vec.fill(n){Bits(width = dw)}
@@ -201,8 +198,8 @@ class Slave extends AXISlave
   rvalid(2) := top.io.mem.req_data.valid
   when (ren(2) && rvalid(2)) { out_count := out_count + UInt(1) }
 
-  // read cr3 -> error mode (nonblocking)
-  rdata(3) := Cat(top.io.mem.req_cmd.valid, tagq.io.enq.ready, top.io.debug.error_mode)
+  // read cr3 -> debug signals (nonblocking)
+  rdata(3) := Cat(top.io.mem.req_cmd.valid, tagq.io.enq.ready)
   rvalid(3) := Bool(true)
 
   // writes to cr2, cr3 ignored
diff --git a/uncore b/uncore
index 0cc26c50..3dd49c34 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 0cc26c501efad36463e3195f3b0992ed31833e73
+Subproject commit 3dd49c34aad2256865fb3500fcbf1626d3b1b01b