riscv/rocket-chip
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update to new isa; disable vector tests

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This commit is contained in:
Andrew Waterman 2013-09-12 17:03:38 -07:00
parent b42e140e05
commit fbdbb01232
8 changed files with 25 additions and 39 deletions
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22
Makefrag
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@ -20,8 +20,6 @@ src_path = src/main/scala
tstdir = $(base_dir)/riscv-tests/isa tstdir = $(base_dir)/riscv-tests/isa
asm_p_tests = \ asm_p_tests = \
rv64si-pm-ipi \
rv64ui-pm-lrsc \
rv64ui-p-add \ rv64ui-p-add \
rv64ui-p-addi \ rv64ui-p-addi \
rv64ui-p-amoadd_d \ rv64ui-p-amoadd_d \
@ -30,6 +28,8 @@ asm_p_tests = \
rv64ui-p-amoand_w \ rv64ui-p-amoand_w \
rv64ui-p-amoor_d \ rv64ui-p-amoor_d \
rv64ui-p-amoor_w \ rv64ui-p-amoor_w \
rv64ui-p-amoxor_d \
rv64ui-p-amoxor_w \
rv64ui-p-amoswap_d \ rv64ui-p-amoswap_d \
rv64ui-p-amoswap_w \ rv64ui-p-amoswap_w \
rv64ui-p-amomax_d \ rv64ui-p-amomax_d \
@ -63,8 +63,6 @@ asm_p_tests = \
rv64ui-p-j \ rv64ui-p-j \
rv64ui-p-jal \ rv64ui-p-jal \
rv64ui-p-jalr \ rv64ui-p-jalr \
rv64ui-p-jalr_j \
rv64ui-p-jalr_r \
rv64ui-p-lb \ rv64ui-p-lb \
rv64ui-p-lbu \ rv64ui-p-lbu \
rv64ui-p-ld \ rv64ui-p-ld \
@ -113,6 +111,8 @@ asm_p_tests = \
rv64uf-p-fmin \ rv64uf-p-fmin \
rv64uf-p-fmadd \ rv64uf-p-fmadd \
rv64uf-p-structural \ rv64uf-p-structural \
rv64si-pm-ipi \
rv64ui-pm-lrsc \
asm_v_tests = \ asm_v_tests = \
rv64ui-v-add \ rv64ui-v-add \
@ -123,6 +123,8 @@ asm_v_tests = \
rv64ui-v-amoand_w \ rv64ui-v-amoand_w \
rv64ui-v-amoor_d \ rv64ui-v-amoor_d \
rv64ui-v-amoor_w \ rv64ui-v-amoor_w \
rv64ui-v-amoxor_d \
rv64ui-v-amoxor_w \
rv64ui-v-amoswap_d \ rv64ui-v-amoswap_d \
rv64ui-v-amoswap_w \ rv64ui-v-amoswap_w \
rv64ui-v-amomax_d \ rv64ui-v-amomax_d \
@ -156,8 +158,6 @@ asm_v_tests = \
rv64ui-v-j \ rv64ui-v-j \
rv64ui-v-jal \ rv64ui-v-jal \
rv64ui-v-jalr \ rv64ui-v-jalr \
rv64ui-v-jalr_j \
rv64ui-v-jalr_r \
rv64ui-v-lb \ rv64ui-v-lb \
rv64ui-v-lbu \ rv64ui-v-lbu \
rv64ui-v-ld \ rv64ui-v-ld \
@ -503,11 +503,11 @@ bmarks = \
dgemm.riscv \ dgemm.riscv \
dhrystone.riscv \ dhrystone.riscv \
spmv.riscv \ spmv.riscv \
vec-vvadd.riscv \ #vec-vvadd.riscv \
vec-cmplxmult.riscv \ #vec-cmplxmult.riscv \
vec-matmul.riscv \ #vec-matmul.riscv \
mt-vvadd.riscv \ #mt-vvadd.riscv \
mt-matmul.riscv \ #mt-matmul.riscv \
vec_bmarkdir = $(base_dir)/../../riscv-app/misc/build vec_bmarkdir = $(base_dir)/../../riscv-app/misc/build
vec_bmarks = \ vec_bmarks = \

7
csrc/emulator.cc
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@ -125,13 +125,6 @@ int main(int argc, char** argv)
tile.Top__io_host_out_ready = LIT<1>(1); tile.Top__io_host_out_ready = LIT<1>(1);
} }
if (tile.Top__io_debug_error_mode.lo_word())
{
failure = "entered error mode";
break;
}
if (log) if (log)
tile.print(stderr); tile.print(stderr);

4
emulator/Makefile
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@ -106,6 +106,6 @@ run-bmarks-test-debug: $(addprefix output/, $(addsuffix .vpd, $(bmarks)))
run-mt-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(mt_bmarks))) run-mt-tests-debug: $(addprefix output/, $(addsuffix .vpd, $(mt_bmarks)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $(patsubst %.vpd,%.out,$^); echo;
run: run-asm-tests run-vecasm-tests run-vecasm-timer-tests run-bmarks-test run: run-asm-tests run-bmarks-test #run-vecasm-tests run-vecasm-timer-tests
run-debug: run-asm-tests-debug run-vecasm-tests-debug run-vecasm-timer-tests-debug run-bmarks-test-debug run-debug: run-asm-tests-debug run-bmarks-test-debug #run-vecasm-tests-debug run-vecasm-timer-tests-debug
run-fast: $(addprefix output/, $(addsuffix .run, $(asm_p_tests) $(asm_v_tests) $(bmarks))) run-fast: $(addprefix output/, $(addsuffix .run, $(asm_p_tests) $(asm_v_tests) $(bmarks)))

2
riscv-tests

@ -1 +1 @@
Subproject commit c31d7c5eb4109fdcce58d27b132e20596ece2d07 Subproject commit 728924ea6db6f6c3ee11554c3ad79d9bdabbe57e

2
rocket

@ -1 +1 @@
Subproject commit b239d7f9ad8c127c3ef6f9912ad0bf5771817fe5 Subproject commit 9b3b586bbbe38c7b455615a073716f6f6946df44

14
src/main/scala/RocketChip.scala
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@ -145,7 +145,6 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
{ {
implicit val tl = conf.tl implicit val tl = conf.tl
val io = new Bundle { val io = new Bundle {
val debug = new DebugIO()
val host = new HostIO(htif_width) val host = new HostIO(htif_width)
val mem = new ioMem val mem = new ioMem
val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
@ -212,7 +211,6 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
} }
class TopIO(htifWidth: Int) extends Bundle { class TopIO(htifWidth: Int) extends Bundle {
val debug = new DebugIO
val host = new HostIO(htifWidth) val host = new HostIO(htifWidth)
val mem = new ioMem val mem = new ioMem
} }
@ -259,7 +257,6 @@ class Top extends Module {
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
val uncore = Module(new Uncore(HTIF_WIDTH, tileList)) val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
var error_mode = Bool(false)
for (i <- 0 until uc.nTiles) { for (i <- 0 until uc.nTiles) {
val hl = uncore.io.htif(i) val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i) val tl = uncore.io.tiles(i)
@ -270,11 +267,11 @@ class Top extends Module {
tile.io.tilelink <> tl tile.io.tilelink <> tl
il := hl.reset il := hl.reset
tile.io.host.reset := Reg(next=Reg(next=hl.reset)) tile.io.host.reset := Reg(next=Reg(next=hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req) tile.io.host.pcr_req <> Queue(hl.pcr_req, 1)
hl.pcr_rep <> Queue(tile.io.host.pcr_rep) tile.io.host.id := i
hl.ipi_req <> Queue(tile.io.host.ipi_req) hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep) hl.ipi_req <> Queue(tile.io.host.ipi_req, 1)
error_mode = error_mode || Reg(next=tile.io.host.debug.error_mode) tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1)
} }
io.host <> uncore.io.host io.host <> uncore.io.host
@ -286,5 +283,4 @@ class Top extends Module {
io.mem_backup_en <> uncore.io.mem_backup_en io.mem_backup_en <> uncore.io.mem_backup_en
io.mem <> uncore.io.mem io.mem <> uncore.io.mem
io.debug.error_mode := error_mode
} }

11
src/main/scala/fpga.scala
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@ -39,7 +39,6 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
{ {
implicit val (tl, ln) = (conf.tl, conf.tl.ln) implicit val (tl, ln) = (conf.tl, conf.tl.ln)
val io = new Bundle { val io = new Bundle {
val debug = new DebugIO()
val host = new HostIO(htif_width) val host = new HostIO(htif_width)
val mem = new ioMem val mem = new ioMem
val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
@ -103,7 +102,6 @@ class FPGATop extends Module {
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
val uncore = Module(new FPGAUncore(htif_width, tileList)) val uncore = Module(new FPGAUncore(htif_width, tileList))
io.debug.error_mode := Bool(false)
for (i <- 0 until uc.nTiles) { for (i <- 0 until uc.nTiles) {
val hl = uncore.io.htif(i) val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i) val tl = uncore.io.tiles(i)
@ -114,13 +112,12 @@ class FPGATop extends Module {
tile.io.tilelink <> tl tile.io.tilelink <> tl
il := hl.reset il := hl.reset
tile.io.host.id := UInt(i)
tile.io.host.reset := Reg(next=Reg(next=hl.reset)) tile.io.host.reset := Reg(next=Reg(next=hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req) tile.io.host.pcr_req <> Queue(hl.pcr_req)
hl.pcr_rep <> Queue(tile.io.host.pcr_rep) hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
hl.ipi_req <> Queue(tile.io.host.ipi_req) hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep) tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
when (tile.io.host.debug.error_mode) { io.debug.error_mode := Bool(true) }
} }
io.host <> uncore.io.host io.host <> uncore.io.host
@ -144,7 +141,7 @@ class Slave extends AXISlave
val memw = top.io.mem.resp.bits.data.getWidth val memw = top.io.mem.resp.bits.data.getWidth
val htifw = top.io.host.in.bits.getWidth val htifw = top.io.host.in.bits.getWidth
val n = 4 // htif, mem req/read data, mem write data, error mode val n = 4
def wen(i: Int) = io.in.valid && io.addr(log2Up(n)-1,0) === UInt(i) def wen(i: Int) = io.in.valid && io.addr(log2Up(n)-1,0) === UInt(i)
def ren(i: Int) = io.out.ready && io.addr(log2Up(n)-1,0) === UInt(i) def ren(i: Int) = io.out.ready && io.addr(log2Up(n)-1,0) === UInt(i)
val rdata = Vec.fill(n){Bits(width = dw)} val rdata = Vec.fill(n){Bits(width = dw)}
@ -201,8 +198,8 @@ class Slave extends AXISlave
rvalid(2) := top.io.mem.req_data.valid rvalid(2) := top.io.mem.req_data.valid
when (ren(2) && rvalid(2)) { out_count := out_count + UInt(1) } when (ren(2) && rvalid(2)) { out_count := out_count + UInt(1) }
// read cr3 -> error mode (nonblocking) // read cr3 -> debug signals (nonblocking)
rdata(3) := Cat(top.io.mem.req_cmd.valid, tagq.io.enq.ready, top.io.debug.error_mode) rdata(3) := Cat(top.io.mem.req_cmd.valid, tagq.io.enq.ready)
rvalid(3) := Bool(true) rvalid(3) := Bool(true)
// writes to cr2, cr3 ignored // writes to cr2, cr3 ignored

2
uncore

@ -1 +1 @@
Subproject commit 0cc26c501efad36463e3195f3b0992ed31833e73 Subproject commit 3dd49c34aad2256865fb3500fcbf1626d3b1b01b