riscv/rocket-chip
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Revert "rocket: link itim to its cpu"

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This reverts commit 48390ed604.
This commit is contained in:
Wesley W. Terpstra
2017-06-28 21:28:08 -07:00
parent 6e5a4c687f
commit fbcd6f0eb2
3 changed files with 5 additions and 14 deletions
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7
src/main/scala/rocket/Frontend.scala
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@ -53,9 +53,9 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
val perf = new FrontendPerfEvents().asInput
}
class Frontend(val icacheParams: ICacheParams, hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule {
class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
lazy val module = new FrontendModule(this)
val icache = LazyModule(new ICache(icacheParams, hartid, owner))
val icache = LazyModule(new ICache(icacheParams, hartid))
val masterNode = TLOutputNode()
val slaveNode = TLInputNode()
@ -185,8 +185,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
val module: HasICacheFrontendModule
def itimOwner : Option[Device] = None
val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int, itimOwner))
val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int))
val hartid: Int
tileBus.node := frontend.masterNode
nPTWPorts += 1