From fbcd6f0eb2b874de818c8f4489dc4d0d48661743 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 28 Jun 2017 21:28:08 -0700
Subject: [PATCH] Revert "rocket: link itim to its cpu"

This reverts commit 48390ed604e12dbcb1b119cb2d4eb1c645ea8f7e.
---
 src/main/scala/rocket/Frontend.scala    |  7 +++----
 src/main/scala/rocket/ICache.scala      | 11 ++---------
 src/main/scala/rocket/RocketTiles.scala |  1 -
 3 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala
index baf45dc7..44f51d32 100644
--- a/src/main/scala/rocket/Frontend.scala
+++ b/src/main/scala/rocket/Frontend.scala
@@ -53,9 +53,9 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
   val perf = new FrontendPerfEvents().asInput
 }
 
-class Frontend(val icacheParams: ICacheParams, hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule {
+class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
   lazy val module = new FrontendModule(this)
-  val icache = LazyModule(new ICache(icacheParams, hartid, owner))
+  val icache = LazyModule(new ICache(icacheParams, hartid))
   val masterNode = TLOutputNode()
   val slaveNode = TLInputNode()
 
@@ -185,8 +185,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
 /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
 trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
   val module: HasICacheFrontendModule
-  def itimOwner : Option[Device] = None
-  val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int, itimOwner))
+  val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int))
   val hartid: Int
   tileBus.node := frontend.masterNode
   nPTWPorts += 1
diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala
index ec093623..dfb240f4 100644
--- a/src/main/scala/rocket/ICache.scala
+++ b/src/main/scala/rocket/ICache.scala
@@ -35,19 +35,12 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
   val addr = UInt(width = vaddrBits)
 }
 
-class ICache(val icacheParams: ICacheParams, val hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule {
+class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parameters) extends LazyModule {
   lazy val module = new ICacheModule(this)
   val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
 
-  val device = new SimpleDevice("itim", Seq("sifive,itim0")) {
-      override def describe(resources: ResourceBindings): Description = {
-      val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label))))
-      val Description(name, mapping) = super.describe(resources)
-      Description(name, mapping ++ extra)
-    }
-  }
-
   val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
+  val device = new SimpleDevice("itim", Seq("sifive,itim0"))
   val slaveNode = icacheParams.itimAddr.map { itimAddr =>
     val wordBytes = icacheParams.fetchBytes
     TLManagerNode(Seq(TLManagerPortParameters(
diff --git a/src/main/scala/rocket/RocketTiles.scala b/src/main/scala/rocket/RocketTiles.scala
index ab118915..4e5fccad 100644
--- a/src/main/scala/rocket/RocketTiles.scala
+++ b/src/main/scala/rocket/RocketTiles.scala
@@ -91,7 +91,6 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
   }
 
   override def dtimOwner = Some(cpuDevice)
-  override def itimOwner = Some(cpuDevice)
 
   val intcDevice = new Device {
     def describe(resources: ResourceBindings): Description = {