riscv/rocket-chip
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extra devices should get elaborated in a single build function

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This commit is contained in:
Howard Mao
2016-08-19 18:26:34 -07:00
parent 8d6f080ed0
commit f9ea14b4c2
4 changed files with 74 additions and 75 deletions
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20
src/main/scala/rocketchip/TestConfigs.scala
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@ -11,6 +11,7 @@ import uncore.unittests._
import junctions._
import junctions.unittests._
import scala.collection.mutable.LinkedHashSet
import scala.collection.immutable.HashMap
import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
import scala.math.max
import coreplex._
@ -183,21 +184,20 @@ class WithBusMasterTest extends Config(
case BuildGroundTest =>
(p: Parameters) => Module(new BusMasterTest()(p))
case ExtraDevices => {
class BusMasterDevice extends Device {
def hasClientPort = true
def hasMMIOPort = true
class BusMasterDevice extends DeviceBlock {
def nClientPorts = 1
def addrMapEntries = Seq(
AddrMapEntry("busmaster", MemSize(4096, MemAttr(AddrMapProt.RW))))
def builder(
mmioPort: Option[ClientUncachedTileLinkIO],
clientPort: Option[ClientUncachedTileLinkIO],
mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
clientPorts: Seq[ClientUncachedTileLinkIO],
extra: Bundle, p: Parameters) {
val busmaster = Module(new ExampleBusMaster()(p))
busmaster.io.mmio <> mmioPort.get
clientPort.get <> busmaster.io.mem
busmaster.io.mmio <> mmioPorts("busmaster")
clientPorts.head <> busmaster.io.mem
}
override def addrMapEntry =
AddrMapEntry("busmaster", MemSize(4096, MemAttr(AddrMapProt.RW)))
}
Seq(new BusMasterDevice)
new BusMasterDevice
}
case _ => throw new CDEMatchError
})