riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...))

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-11-22 18:46:11 -08:00
parent d9a203b0f0
commit f9de7173cc
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/util/PositionalMultiQueue.scala
View File

@ -35,8 +35,8 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T],
val empty = RegInit(Vec.fill(params.ways) { Bool(true) })
val head = Reg(Vec(params.ways, UInt(width = log2Up(params.positions))))
val tail = Reg(Vec(params.ways, UInt(width = log2Up(params.positions))))
val next = Reg(Vec(params.positions, UInt(width = log2Up(params.positions))))
val data = Reg(Vec(params.positions, params.gen))
val next = Mem(params.positions, UInt(width = log2Up(params.positions)))
val data = Mem(params.positions, params.gen)
// optimized away for synthesis; used to confirm invariant
val guard = RegInit(Vec.fill(params.positions) { Bool(false) })