From f9de7173cce9b75843ec83390d37c5aacbfe2e1f Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 22 Nov 2016 18:46:11 -0800 Subject: [PATCH] PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...)) --- src/main/scala/util/PositionalMultiQueue.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/util/PositionalMultiQueue.scala b/src/main/scala/util/PositionalMultiQueue.scala index eadb1f88..b9c00b9b 100644 --- a/src/main/scala/util/PositionalMultiQueue.scala +++ b/src/main/scala/util/PositionalMultiQueue.scala @@ -35,8 +35,8 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T], val empty = RegInit(Vec.fill(params.ways) { Bool(true) }) val head = Reg(Vec(params.ways, UInt(width = log2Up(params.positions)))) val tail = Reg(Vec(params.ways, UInt(width = log2Up(params.positions)))) - val next = Reg(Vec(params.positions, UInt(width = log2Up(params.positions)))) - val data = Reg(Vec(params.positions, params.gen)) + val next = Mem(params.positions, UInt(width = log2Up(params.positions))) + val data = Mem(params.positions, params.gen) // optimized away for synthesis; used to confirm invariant val guard = RegInit(Vec.fill(params.positions) { Bool(false) })