don't use secondary external address map; collapse submap instead

junctions/src/main/scala/addrmap.scala

@@ -74,7 +74,10 @@ object AddrMap {
   def apply(elems: AddrMapEntry*): AddrMap = new AddrMap(elems)
 }
 
-class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) extends MemRegion {
+class AddrMap(
+    entriesIn: Seq[AddrMapEntry],
+    val start: BigInt = BigInt(0),
+    val collapse: Boolean = false) extends MemRegion {
   private val slavePorts = HashMap[String, Int]()
   private val mapping = HashMap[String, MemRegion]()
 
@@ -99,19 +102,27 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
 
       r match {
         case r: AddrMap =>
-          val subMap = new AddrMap(r.entries, base)
+          val subMap = new AddrMap(r.entries, base, r.collapse)
           rebasedEntries += AddrMapEntry(name, subMap)
           mapping += name -> subMap
           mapping ++= subMap.mapping.map { case (k, v) => s"$name:$k" -> v }
-          slavePorts ++= subMap.slavePorts.map { case (k, v) => s"$name:$k" -> (ind + v) }
+          if (r.collapse) {
+            slavePorts += (name -> ind)
+            ind += 1
+          } else {
+            slavePorts ++= subMap.slavePorts.map {
+              case (k, v) => s"$name:$k" -> (ind + v)
+            }
+            ind += r.numSlaves
+          }
         case _ =>
           val e = MemRange(base, r.size, r.attr)
           rebasedEntries += AddrMapEntry(name, e)
           mapping += name -> e
           slavePorts += name -> ind
+          ind += r.numSlaves
       }
 
-      ind += r.numSlaves
       base += r.size
       prot |= r.attr.prot
       cacheable &&= r.attr.cacheable

src/main/scala/Configs.scala

@@ -36,12 +36,17 @@ class BaseConfig extends Config (
       entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
       new AddrMap(entries)
     }
+    lazy val externalAddrMap = new AddrMap(
+      site(ExtraDevices).map(_.addrMapEntry) ++
+      site(ExtMMIOPorts),
+      start = BigInt("50000000", 16),
+      collapse = true)
     lazy val globalAddrMap = {
       val memBase = 0x80000000L
       val memSize = 0x10000000L
 
       val intern = AddrMapEntry("int", internalIOAddrMap)
-      val extern = AddrMapEntry("ext", site(ExtAddrMap).toRange)
+      val extern = AddrMapEntry("ext", externalAddrMap)
       val ioMap = if (site(ExportMMIOPort)) AddrMap(intern, extern) else AddrMap(intern)
 
       val addrMap = AddrMap(
@@ -54,7 +59,6 @@ class BaseConfig extends Config (
     }
     def makeConfigString() = {
       val addrMap = globalAddrMap
-      val extAddrMap = site(ExtAddrMap)
       val plicAddr = addrMap("io:int:plic").start
       val prciAddr = addrMap("io:int:prci").start
       val plicInfo = site(PLICKey)
@@ -101,7 +105,7 @@ class BaseConfig extends Config (
       }
       for (device <- site(ExtraDevices)) {
         val deviceName = device.addrMapEntry.name
-        val deviceRegion = extAddrMap(deviceName)
+        val deviceRegion = addrMap("io:ext:" + deviceName)
         res.append(device.makeConfigString(deviceRegion))
       }
       res append  "};\n"
@@ -237,10 +241,6 @@ class BaseConfig extends Config (
       case ExtraDevices => Nil
       case ExtraTopPorts => (p: Parameters) => new Bundle
       case ExtMMIOPorts => Nil
-      case ExtAddrMap => new AddrMap(
-        site(ExtraDevices).map(_.addrMapEntry) ++
-        site(ExtMMIOPorts),
-        start = BigInt("50000000", 16))
       case NExtMMIOAXIChannels => 0
       case NExtMMIOAHBChannels => 0
       case NExtMMIOTLChannels  => 0

src/main/scala/RocketChip.scala

@@ -40,7 +40,6 @@ case object AsyncMMIOChannels extends Field[Boolean]
 
 /** External address map settings */
 case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]]
-case object ExtAddrMap extends Field[AddrMap]
 
 /** Utility trait for quick access to some relevant parameters */
 trait HasTopLevelParameters {
@@ -225,7 +224,7 @@ class Periphery(implicit val p: Parameters) extends Module
   }
 
   def buildMMIONetwork(implicit p: Parameters) = {
-    val extAddrMap = p(ExtAddrMap)
+    val extAddrMap = p(GlobalAddrMap).subMap("io:ext")
 
     val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, extAddrMap))
     mmioNetwork.io.in.head <> io.mmio_in.get

src/main/scala/TestConfigs.scala

@@ -69,10 +69,8 @@ class WithComparator extends Config(
     case BuildGroundTest =>
       (p: Parameters) => Module(new ComparatorCore()(p))
     case ComparatorKey => ComparatorParameters(
-      targets    = Seq(
+      targets    = Seq("mem", "io:ext:testram").map(name =>
-        site(GlobalAddrMap)("mem"),
+                    site(GlobalAddrMap)(name).start.longValue),
-        site(ExtAddrMap)("testram"))
-          .map(entry => entry.start.longValue),
       width      = 8,
       operations = 1000,
       atomics    = site(UseAtomics),

uncore/src/main/scala/tilelink/Interconnect.scala

@@ -276,7 +276,7 @@ class TileLinkRecursiveInterconnect(val nInner: Int, addrMap: AddrMap)
           xbarOut.acquire.ready := Bool(false)
           xbarOut.grant.valid := Bool(false)
           None
-        case submap: AddrMap =>
+        case submap: AddrMap if !submap.collapse =>
           val ic = Module(new TileLinkRecursiveInterconnect(1, submap))
           ic.io.in.head <> xbarOut
           ic.io.out