From f95d319162300933edf1d5ce387f3b702c7686c3 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 9 Aug 2016 22:19:08 -0700 Subject: [PATCH] don't use secondary external address map; collapse submap instead --- junctions/src/main/scala/addrmap.scala | 19 +++++++++++++++---- src/main/scala/Configs.scala | 14 +++++++------- src/main/scala/RocketChip.scala | 3 +-- src/main/scala/TestConfigs.scala | 6 ++---- .../main/scala/tilelink/Interconnect.scala | 2 +- 5 files changed, 26 insertions(+), 18 deletions(-) diff --git a/junctions/src/main/scala/addrmap.scala b/junctions/src/main/scala/addrmap.scala index da477316..e796f8df 100644 --- a/junctions/src/main/scala/addrmap.scala +++ b/junctions/src/main/scala/addrmap.scala @@ -74,7 +74,10 @@ object AddrMap { def apply(elems: AddrMapEntry*): AddrMap = new AddrMap(elems) } -class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) extends MemRegion { +class AddrMap( + entriesIn: Seq[AddrMapEntry], + val start: BigInt = BigInt(0), + val collapse: Boolean = false) extends MemRegion { private val slavePorts = HashMap[String, Int]() private val mapping = HashMap[String, MemRegion]() @@ -99,19 +102,27 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten r match { case r: AddrMap => - val subMap = new AddrMap(r.entries, base) + val subMap = new AddrMap(r.entries, base, r.collapse) rebasedEntries += AddrMapEntry(name, subMap) mapping += name -> subMap mapping ++= subMap.mapping.map { case (k, v) => s"$name:$k" -> v } - slavePorts ++= subMap.slavePorts.map { case (k, v) => s"$name:$k" -> (ind + v) } + if (r.collapse) { + slavePorts += (name -> ind) + ind += 1 + } else { + slavePorts ++= subMap.slavePorts.map { + case (k, v) => s"$name:$k" -> (ind + v) + } + ind += r.numSlaves + } case _ => val e = MemRange(base, r.size, r.attr) rebasedEntries += AddrMapEntry(name, e) mapping += name -> e slavePorts += name -> ind + ind += r.numSlaves } - ind += r.numSlaves base += r.size prot |= r.attr.prot cacheable &&= r.attr.cacheable diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 6e3ea029..23d4c533 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -36,12 +36,17 @@ class BaseConfig extends Config ( entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW))) new AddrMap(entries) } + lazy val externalAddrMap = new AddrMap( + site(ExtraDevices).map(_.addrMapEntry) ++ + site(ExtMMIOPorts), + start = BigInt("50000000", 16), + collapse = true) lazy val globalAddrMap = { val memBase = 0x80000000L val memSize = 0x10000000L val intern = AddrMapEntry("int", internalIOAddrMap) - val extern = AddrMapEntry("ext", site(ExtAddrMap).toRange) + val extern = AddrMapEntry("ext", externalAddrMap) val ioMap = if (site(ExportMMIOPort)) AddrMap(intern, extern) else AddrMap(intern) val addrMap = AddrMap( @@ -54,7 +59,6 @@ class BaseConfig extends Config ( } def makeConfigString() = { val addrMap = globalAddrMap - val extAddrMap = site(ExtAddrMap) val plicAddr = addrMap("io:int:plic").start val prciAddr = addrMap("io:int:prci").start val plicInfo = site(PLICKey) @@ -101,7 +105,7 @@ class BaseConfig extends Config ( } for (device <- site(ExtraDevices)) { val deviceName = device.addrMapEntry.name - val deviceRegion = extAddrMap(deviceName) + val deviceRegion = addrMap("io:ext:" + deviceName) res.append(device.makeConfigString(deviceRegion)) } res append "};\n" @@ -237,10 +241,6 @@ class BaseConfig extends Config ( case ExtraDevices => Nil case ExtraTopPorts => (p: Parameters) => new Bundle case ExtMMIOPorts => Nil - case ExtAddrMap => new AddrMap( - site(ExtraDevices).map(_.addrMapEntry) ++ - site(ExtMMIOPorts), - start = BigInt("50000000", 16)) case NExtMMIOAXIChannels => 0 case NExtMMIOAHBChannels => 0 case NExtMMIOTLChannels => 0 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 137f32c9..721fab91 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -40,7 +40,6 @@ case object AsyncMMIOChannels extends Field[Boolean] /** External address map settings */ case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]] -case object ExtAddrMap extends Field[AddrMap] /** Utility trait for quick access to some relevant parameters */ trait HasTopLevelParameters { @@ -225,7 +224,7 @@ class Periphery(implicit val p: Parameters) extends Module } def buildMMIONetwork(implicit p: Parameters) = { - val extAddrMap = p(ExtAddrMap) + val extAddrMap = p(GlobalAddrMap).subMap("io:ext") val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, extAddrMap)) mmioNetwork.io.in.head <> io.mmio_in.get diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala index f0256238..4a2d28b7 100644 --- a/src/main/scala/TestConfigs.scala +++ b/src/main/scala/TestConfigs.scala @@ -69,10 +69,8 @@ class WithComparator extends Config( case BuildGroundTest => (p: Parameters) => Module(new ComparatorCore()(p)) case ComparatorKey => ComparatorParameters( - targets = Seq( - site(GlobalAddrMap)("mem"), - site(ExtAddrMap)("testram")) - .map(entry => entry.start.longValue), + targets = Seq("mem", "io:ext:testram").map(name => + site(GlobalAddrMap)(name).start.longValue), width = 8, operations = 1000, atomics = site(UseAtomics), diff --git a/uncore/src/main/scala/tilelink/Interconnect.scala b/uncore/src/main/scala/tilelink/Interconnect.scala index 353dbb80..7e3aaaaf 100644 --- a/uncore/src/main/scala/tilelink/Interconnect.scala +++ b/uncore/src/main/scala/tilelink/Interconnect.scala @@ -276,7 +276,7 @@ class TileLinkRecursiveInterconnect(val nInner: Int, addrMap: AddrMap) xbarOut.acquire.ready := Bool(false) xbarOut.grant.valid := Bool(false) None - case submap: AddrMap => + case submap: AddrMap if !submap.collapse => val ic = Module(new TileLinkRecursiveInterconnect(1, submap)) ic.io.in.head <> xbarOut ic.io.out