riscv/rocket-chip
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don't use secondary external address map; collapse submap instead

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This commit is contained in:
Howard Mao
2016-08-09 22:19:08 -07:00
parent 2645f74af2
commit f95d319162
5 changed files with 26 additions and 18 deletions
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19
junctions/src/main/scala/addrmap.scala
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@@ -74,7 +74,10 @@ object AddrMap {
def apply(elems: AddrMapEntry*): AddrMap = new AddrMap(elems)
}
class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) extends MemRegion {
class AddrMap(
entriesIn: Seq[AddrMapEntry],
val start: BigInt = BigInt(0),
val collapse: Boolean = false) extends MemRegion {
private val slavePorts = HashMap[String, Int]()
private val mapping = HashMap[String, MemRegion]()
@@ -99,19 +102,27 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
r match {
case r: AddrMap =>
val subMap = new AddrMap(r.entries, base)
val subMap = new AddrMap(r.entries, base, r.collapse)
rebasedEntries += AddrMapEntry(name, subMap)
mapping += name -> subMap
mapping ++= subMap.mapping.map { case (k, v) => s"$name:$k" -> v }
slavePorts ++= subMap.slavePorts.map { case (k, v) => s"$name:$k" -> (ind + v) }
if (r.collapse) {
slavePorts += (name -> ind)
ind += 1
} else {
slavePorts ++= subMap.slavePorts.map {
case (k, v) => s"$name:$k" -> (ind + v)
}
ind += r.numSlaves
}
case _ =>
val e = MemRange(base, r.size, r.attr)
rebasedEntries += AddrMapEntry(name, e)
mapping += name -> e
slavePorts += name -> ind
ind += r.numSlaves
}
ind += r.numSlaves
base += r.size
prot |= r.attr.prot
cacheable &&= r.attr.cacheable