riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Chisel3 compatibility: use BitPat for don't-cares

Browse Source 
Also, call the UInt factory instead of the Bits one, for good measure.
This commit is contained in:
Andrew Waterman 2015-07-28 02:46:23 -07:00
parent 0e06c941df
commit f8ec6d6393
1 changed files with 34 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
uncore/src/main/scala/consts.scala
View File

@ -8,42 +8,42 @@ import Chisel._
object MemoryOpConstants extends MemoryOpConstants object MemoryOpConstants extends MemoryOpConstants
trait MemoryOpConstants { trait MemoryOpConstants {
val MT_SZ = 3 val MT_SZ = 3
val MT_X = Bits("b???") val MT_X = BitPat("b???")
val MT_B = Bits("b000") val MT_B = UInt("b000")
val MT_H = Bits("b001") val MT_H = UInt("b001")
val MT_W = Bits("b010") val MT_W = UInt("b010")
val MT_D = Bits("b011") val MT_D = UInt("b011")
val MT_BU = Bits("b100") val MT_BU = UInt("b100")
val MT_HU = Bits("b101") val MT_HU = UInt("b101")
val MT_WU = Bits("b110") val MT_WU = UInt("b110")
val MT_Q = Bits("b111") val MT_Q = UInt("b111")
val NUM_XA_OPS = 9 val NUM_XA_OPS = 9
val M_SZ = 5 val M_SZ = 5
val M_X = Bits("b?????"); val M_X = BitPat("b?????");
val M_XRD = Bits("b00000"); // int load val M_XRD = UInt("b00000"); // int load
val M_XWR = Bits("b00001"); // int store val M_XWR = UInt("b00001"); // int store
val M_PFR = Bits("b00010"); // prefetch with intent to read val M_PFR = UInt("b00010"); // prefetch with intent to read
val M_PFW = Bits("b00011"); // prefetch with intent to write val M_PFW = UInt("b00011"); // prefetch with intent to write
val M_XA_SWAP = Bits("b00100"); val M_XA_SWAP = UInt("b00100");
val M_NOP = Bits("b00101"); val M_NOP = UInt("b00101");
val M_XLR = Bits("b00110"); val M_XLR = UInt("b00110");
val M_XSC = Bits("b00111"); val M_XSC = UInt("b00111");
val M_XA_ADD = Bits("b01000"); val M_XA_ADD = UInt("b01000");
val M_XA_XOR = Bits("b01001"); val M_XA_XOR = UInt("b01001");
val M_XA_OR = Bits("b01010"); val M_XA_OR = UInt("b01010");
val M_XA_AND = Bits("b01011"); val M_XA_AND = UInt("b01011");
val M_XA_MIN = Bits("b01100"); val M_XA_MIN = UInt("b01100");
val M_XA_MAX = Bits("b01101"); val M_XA_MAX = UInt("b01101");
val M_XA_MINU = Bits("b01110"); val M_XA_MINU = UInt("b01110");
val M_XA_MAXU = Bits("b01111"); val M_XA_MAXU = UInt("b01111");
val M_FLUSH = Bits("b10000") // write back dirty data and cede R/W permissions val M_FLUSH = UInt("b10000") // write back dirty data and cede R/W permissions
val M_PRODUCE = Bits("b10001") // write back dirty data and cede W permissions val M_PRODUCE = UInt("b10001") // write back dirty data and cede W permissions
val M_CLEAN = Bits("b10011") // write back dirty data and retain R/W permissions val M_CLEAN = UInt("b10011") // write back dirty data and retain R/W permissions
def isAMO(cmd: Bits) = cmd(3) || cmd === M_XA_SWAP def isAMO(cmd: UInt) = cmd(3) || cmd === M_XA_SWAP
def isPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: Bits) = cmd === M_XRD || cmd === M_XLR || isAMO(cmd) def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || isAMO(cmd)
def isWrite(cmd: Bits) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: Bits) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
} }