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tilelink: RAMModel must support source reuse

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If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
This commit is contained in:
Wesley W. Terpstra 2017-08-07 16:01:15 -07:00
parent aff028f8f0
commit f8b45564d1
1 changed files with 1 additions and 1 deletions
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src/main/scala/tilelink/RAMModel.scala
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@ -223,7 +223,7 @@ class TLRAMModel(log: String = "")(implicit p: Parameters) extends LazyModule
val d_inc = d_inc_bytes.map(_ + d_inc_tree) val d_inc = d_inc_bytes.map(_ + d_inc_tree)
val d_dec = d_dec_bytes.map(_ + d_dec_tree) val d_dec = d_dec_bytes.map(_ + d_dec_tree)
val d_shadow = shadow.map(_.read(d_addr_hi)) val d_shadow = shadow.map(_.read(d_addr_hi))
val d_valid = valid(d.source) val d_valid = valid(d.source) holdUnless d_first
// CRC check // CRC check
val d_crc_reg = Reg(UInt(width = 16)) val d_crc_reg = Reg(UInt(width = 16))