From f8b45564d18ce2a588edbc304f7f602324481b4f Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 7 Aug 2017 16:01:15 -0700 Subject: [PATCH] tilelink: RAMModel must support source reuse If a multibeat response comes back, the source might be reused. If response reordering has made the multibeat response invalid, we need to remember this even if the valid bit is cleared on reuse. --- src/main/scala/tilelink/RAMModel.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/RAMModel.scala b/src/main/scala/tilelink/RAMModel.scala index 0f292961..0d74e8e0 100644 --- a/src/main/scala/tilelink/RAMModel.scala +++ b/src/main/scala/tilelink/RAMModel.scala @@ -223,7 +223,7 @@ class TLRAMModel(log: String = "")(implicit p: Parameters) extends LazyModule val d_inc = d_inc_bytes.map(_ + d_inc_tree) val d_dec = d_dec_bytes.map(_ + d_dec_tree) val d_shadow = shadow.map(_.read(d_addr_hi)) - val d_valid = valid(d.source) + val d_valid = valid(d.source) holdUnless d_first // CRC check val d_crc_reg = Reg(UInt(width = 16))