riscv/rocket-chip
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don't add pending reads if data is already available

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This commit is contained in:
Howard Mao 2016-04-06 15:43:21 -07:00
parent 31e145eaf0
commit f88b6932ce
1 changed files with 3 additions and 2 deletions
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3
uncore/src/main/scala/cache.scala
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@ -927,8 +927,9 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
dropPendingBit(io.data.read) & dropPendingBit(io.data.read) &
dropPendingBitWhenBeatHasData(io.inner.release) & dropPendingBitWhenBeatHasData(io.inner.release) &
dropPendingBitWhenBeatHasData(io.outer.grant)) | dropPendingBitWhenBeatHasData(io.outer.grant)) |
(~ignt_data_ready & (
addPendingBitWhenBeatIsGetOrAtomic(io.inner.acquire) | addPendingBitWhenBeatIsGetOrAtomic(io.inner.acquire) |
addPendingBitWhenBeatHasPartialWritemask(io.inner.acquire) addPendingBitWhenBeatHasPartialWritemask(io.inner.acquire)))
val curr_read_beat = PriorityEncoder(pending_reads) val curr_read_beat = PriorityEncoder(pending_reads)
io.data.read.valid := state === s_busy && pending_reads.orR && !pending_ognt io.data.read.valid := state === s_busy && pending_reads.orR && !pending_ognt
io.data.read.bits.id := UInt(trackerId) io.data.read.bits.id := UInt(trackerId)