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depend on external cde library

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This commit is contained in:
Henry Cook 2015-10-21 18:16:44 -07:00
parent 02d113b39f
commit f8594da1d3
10 changed files with 58 additions and 53 deletions
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1
uncore/src/main/scala/amoalu.scala
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@ -2,6 +2,7 @@
package uncore
import Chisel._
import cde.{Parameters, Field}
abstract class StoreGen(typ: UInt, addr: UInt, dat: UInt) {
val byte = typ === MT_B || typ === MT_BU

1
uncore/src/main/scala/broadcast.scala
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@ -2,6 +2,7 @@
package uncore
import Chisel._
import cde.{Parameters, Field}
case object L2StoreDataQueueDepth extends Field[Int]

5
uncore/src/main/scala/cache.scala
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@ -4,6 +4,7 @@ package uncore
import Chisel._
import scala.reflect.ClassTag
import junctions._
import cde.{Parameters, Field}
case object CacheName extends Field[String]
case object NSets extends Field[Int]
@ -436,7 +437,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends
val s_idle :: s_meta_read :: s_meta_resp :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 5)
val state = Reg(init=s_idle)
val xact = Reg(Bundle(new BufferedReleaseFromSrc()(p.alterPartial({case TLId => p(InnerTLId)}))))
val xact = Reg(new BufferedReleaseFromSrc()(p.alterPartial({case TLId => p(InnerTLId)})))
val xact_way_en = Reg{ Bits(width = nWays) }
val xact_old_meta = Reg{ new L2Metadata }
val coh = xact_old_meta.coh
@ -530,7 +531,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
val state = Reg(init=s_idle)
// State holding transaction metadata
val xact = Reg(Bundle(new BufferedAcquireFromSrc()(p.alterPartial({ case TLId => p(InnerTLId) }))))
val xact = Reg(new BufferedAcquireFromSrc()(p.alterPartial({ case TLId => p(InnerTLId) })))
val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits/8)))
val xact_tag_match = Reg{ Bool() }
val xact_way_en = Reg{ Bits(width = nWays) }

1
uncore/src/main/scala/htif.scala
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@ -5,6 +5,7 @@ package uncore
import Chisel._
import Chisel.ImplicitConversions._
import junctions._
import cde.{Parameters, Field}
case object HtifKey extends Field[HtifParameters]

44
uncore/src/main/scala/metadata.scala
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@ -2,6 +2,7 @@
package uncore
import Chisel._
import cde.{Parameters, Field}
/** Base class to represent coherence information in clients and managers */
abstract class CoherenceMetadata(implicit p: Parameters) extends TLBundle()(p) {
@ -46,14 +47,13 @@ class ClientMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
def makeAcquire(
op_code: UInt,
client_xact_id: UInt,
addr_block: UInt): Acquire = {
Bundle(Acquire(
addr_block: UInt): Acquire =
Acquire(
is_builtin_type = Bool(false),
a_type = co.getAcquireType(op_code, this),
client_xact_id = client_xact_id,
addr_block = addr_block,
union = Cat(op_code, Bool(true)))(p))
}
union = Cat(op_code, Bool(true)))(p)
/** Constructs a Release message based on this metadata on cache control op
*
@ -67,15 +67,14 @@ class ClientMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
client_xact_id: UInt,
addr_block: UInt,
addr_beat: UInt = UInt(0),
data: UInt = UInt(0)): Release = {
Bundle(Release(
data: UInt = UInt(0)): Release =
Release(
voluntary = Bool(true),
r_type = co.getReleaseType(op_code, this),
client_xact_id = client_xact_id,
addr_block = addr_block,
addr_beat = addr_beat,
data = data)(p))
}
data = data)(p)
/** Constructs a Release message based on this metadata on an eviction
*
@ -105,15 +104,14 @@ class ClientMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
def makeRelease(
prb: Probe,
addr_beat: UInt = UInt(0),
data: UInt = UInt(0)): Release = {
Bundle(Release(
data: UInt = UInt(0)): Release =
Release(
voluntary = Bool(false),
r_type = co.getReleaseType(prb, this),
client_xact_id = UInt(0),
addr_block = prb.addr_block,
addr_beat = addr_beat,
data = data)(p))
}
data = data)(p)
/** New metadata after receiving a [[uncore.Grant]]
*
@ -189,7 +187,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
* @param acq Acquire message triggering this Probe
*/
def makeProbe(dst: UInt, acq: AcquireMetadata): ProbeToDst =
Bundle(Probe(dst, co.getProbeType(acq, this), acq.addr_block)(p))
Probe(dst, co.getProbeType(acq, this), acq.addr_block)(p)
/** Construct an appropriate [[uncore.ProbeToDst]] for a given mem op
*
@ -198,7 +196,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
* @param addr_block address of the cache block being probed
*/
def makeProbe(dst: UInt, op_code: UInt, addr_block: UInt): ProbeToDst =
Bundle(Probe(dst, co.getProbeType(op_code, this), addr_block)(p))
Probe(dst, co.getProbeType(op_code, this), addr_block)(p)
/** Construct an appropriate [[uncore.ProbeToDst]] for an eviction
*
@ -213,14 +211,13 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
* @param rel Release message being acknowledged by this Grant
* @param manager_xact_id manager's transaction id
*/
def makeGrant(rel: ReleaseMetadata with HasClientId, manager_xact_id: UInt): GrantToDst = {
Bundle(Grant(
def makeGrant(rel: ReleaseMetadata with HasClientId, manager_xact_id: UInt): GrantToDst =
Grant(
dst = rel.client_id,
is_builtin_type = Bool(true),
g_type = Grant.voluntaryAckType,
client_xact_id = rel.client_xact_id,
manager_xact_id = manager_xact_id)(p))
}
manager_xact_id = manager_xact_id)(p)
/** Construct an appropriate [[uncore.GrantToDst]] to respond to an [[uncore.Acquire]]
*
@ -235,8 +232,8 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
acq: AcquireMetadata with HasClientId,
manager_xact_id: UInt,
addr_beat: UInt = UInt(0),
data: UInt = UInt(0)): GrantToDst = {
Bundle(Grant(
data: UInt = UInt(0)): GrantToDst =
Grant(
dst = acq.client_id,
is_builtin_type = acq.isBuiltInType(),
g_type = Mux(acq.isBuiltInType(),
@ -245,8 +242,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
client_xact_id = acq.client_xact_id,
manager_xact_id = manager_xact_id,
addr_beat = addr_beat,
data = data)(p))
}
data = data)(p)
/** Construct an [[uncore.GrantToDst]] to respond to an [[uncore.Acquire]] with some overrides
*
@ -309,8 +305,8 @@ object ManagerMetadata {
* [[uncore.InnerTLId]] or [[uncore.OuterTLId]].
*/
class HierarchicalMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
val inner: ManagerMetadata = Bundle(new ManagerMetadata()(p.alterPartial({case TLId => p(InnerTLId)})))
val outer: ClientMetadata = Bundle(new ClientMetadata()(p.alterPartial({case TLId => p(OuterTLId)})))
val inner: ManagerMetadata = new ManagerMetadata()(p.alterPartial({case TLId => p(InnerTLId)}))
val outer: ClientMetadata = new ClientMetadata()(p.alterPartial({case TLId => p(OuterTLId)}))
def ===(rhs: HierarchicalMetadata): Bool =
this.inner === rhs.inner && this.outer === rhs.outer
def !=(rhs: HierarchicalMetadata): Bool = !this.===(rhs)

1
uncore/src/main/scala/network.scala
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@ -2,6 +2,7 @@
package uncore
import Chisel._
import cde.{Parameters, Field}
case object LNEndpoints extends Field[Int]
case object LNHeaderBits extends Field[Int]

1
uncore/src/main/scala/rtc.scala
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@ -2,6 +2,7 @@ package uncore
import Chisel._
import junctions._
import cde.{Parameters, Field}
case object RTCPeriod extends Field[Int]

1
uncore/src/main/scala/scr.scala
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@ -2,6 +2,7 @@ package uncore
import Chisel._
import junctions.{SMIIO, MMIOBase}
import cde.Parameters
class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
val rdata = Vec(Bits(INPUT, scrDataBits), nSCR)

3
uncore/src/main/scala/tilelink.scala
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@ -4,6 +4,7 @@ package uncore
import Chisel._
import junctions._
import scala.math.max
import cde.{Parameters, Field}
case object TLId extends Field[String]
case class TLKey(id: String) extends Field[TileLinkParameters]
@ -659,7 +660,7 @@ class GrantMetadata(implicit p: Parameters) extends ManagerToClientChannel()(p)
def isVoluntary(dummy: Int = 0): Bool = isBuiltInType() && (g_type === Grant.voluntaryAckType)
def requiresAck(dummy: Int = 0): Bool = !Bool(tlNetworkPreservesPointToPointOrdering) && !isVoluntary()
def makeFinish(dummy: Int = 0): Finish = {
val f = Wire(Bundle(new Finish))
val f = Wire(new Finish)
f.manager_xact_id := this.manager_xact_id
f
}

7
uncore/src/main/scala/uncore.scala
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@ -2,6 +2,7 @@
package uncore
import Chisel._
import cde.{Parameters, Field}
case object NReleaseTransactors extends Field[Int]
case object NProbeTransactors extends Field[Int]
@ -60,7 +61,7 @@ trait HasCoherenceAgentWiringHelpers {
}
trait HasInnerTLIO extends HasCoherenceAgentParameters {
val inner = Bundle(new ManagerTileLinkIO()(p.alterPartial({case TLId => p(InnerTLId)})))
val inner = new ManagerTileLinkIO()(p.alterPartial({case TLId => p(InnerTLId)}))
val incoherent = Vec(Bool(), inner.tlNCachingClients).asInput
def iacq(dummy: Int = 0) = inner.acquire.bits
def iprb(dummy: Int = 0) = inner.probe.bits
@ -70,13 +71,13 @@ trait HasInnerTLIO extends HasCoherenceAgentParameters {
}
trait HasUncachedOuterTLIO extends HasCoherenceAgentParameters {
val outer = Bundle(new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)})))
val outer = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)}))
def oacq(dummy: Int = 0) = outer.acquire.bits
def ognt(dummy: Int = 0) = outer.grant.bits
}
trait HasCachedOuterTLIO extends HasCoherenceAgentParameters {
val outer = Bundle(new ClientTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)})))
val outer = new ClientTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)}))
def oacq(dummy: Int = 0) = outer.acquire.bits
def oprb(dummy: Int = 0) = outer.probe.bits
def orel(dummy: Int = 0) = outer.release.bits