riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix dcache tag array size

Browse Source
This commit is contained in:
Yunsup Lee 2012-07-16 22:19:03 -07:00
parent e496cd7584
commit f633a55722
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/nbdcache.scala
View File

@ -605,7 +605,7 @@ class MetaDataArrayArray(lines: Int) extends Component {
val permBits = io.req.bits.data.state.width val permBits = io.req.bits.data.state.width
val perms = Mem(lines) { UFix(width = permBits*NWAYS) } val perms = Mem(lines) { UFix(width = permBits*NWAYS) }
val tags = Mem(lines*NWAYS, seqRead = true) { Bits(width = TAG_BITS*NWAYS) } val tags = Mem(lines, seqRead = true) { Bits(width = TAG_BITS*NWAYS) }
val tag = Reg() { Bits() } val tag = Reg() { Bits() }
val raddr = Reg() { Bits() } val raddr = Reg() { Bits() }
val way_en_ = Reg { Bits(width=NWAYS) } val way_en_ = Reg { Bits(width=NWAYS) }