removed ack_required field from grant messages
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6b00e7ff74
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@ -109,7 +109,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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when (io.mem.grant.valid) {
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when (io.mem.grant.valid) {
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mem_acked := Bool(true)
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mem_acked := Bool(true)
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mem_gxid := io.mem.grant.bits.payload.master_xact_id
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mem_gxid := io.mem.grant.bits.payload.master_xact_id
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mem_needs_ack := io.mem.grant.bits.payload.require_ack
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mem_needs_ack := conf.co.requiresAck(io.mem.grant.bits.payload)
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}
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}
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io.mem.grant.ready := Bool(true)
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io.mem.grant.ready := Bool(true)
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when (io.mem.abort.valid) { mem_nacked := Bool(true) }
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when (io.mem.abort.valid) { mem_nacked := Bool(true) }
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@ -238,7 +238,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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val finish_q = (new Queue(1)) { new GrantAck }
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val finish_q = (new Queue(1)) { new GrantAck }
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finish_q.io.enq.valid := refill_done && io.mem.grant.bits.payload.require_ack
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finish_q.io.enq.valid := refill_done && c.co.requiresAck(io.mem.grant.bits.payload)
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finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id
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finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id
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// output signals
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// output signals
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