diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala
index 611beb68..85c6bb50 100644
--- a/rocket/src/main/scala/htif.scala
+++ b/rocket/src/main/scala/htif.scala
@@ -109,7 +109,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
   when (io.mem.grant.valid) { 
     mem_acked := Bool(true)
     mem_gxid := io.mem.grant.bits.payload.master_xact_id
-    mem_needs_ack := io.mem.grant.bits.payload.require_ack  
+    mem_needs_ack := conf.co.requiresAck(io.mem.grant.bits.payload)
   }
   io.mem.grant.ready := Bool(true)
   when (io.mem.abort.valid) { mem_nacked := Bool(true) }
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 5914daac..77ac7f9b 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -238,7 +238,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
   io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
 
   val finish_q = (new Queue(1)) { new GrantAck }
-  finish_q.io.enq.valid := refill_done && io.mem.grant.bits.payload.require_ack
+  finish_q.io.enq.valid := refill_done && c.co.requiresAck(io.mem.grant.bits.payload)
   finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id
 
   // output signals