debug: Remove workaround for Chisel 3 #527
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@ -521,14 +521,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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DMSTATUSRdData.authenticated := true.B // Not implemented
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DMSTATUSRdData.authenticated := true.B // Not implemented
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DMSTATUSRdData.version := 2.U // Version 0.13
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DMSTATUSRdData.version := 2.U // Version 0.13
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// Chisel3 Issue #527 , have to do intermediate assignment.
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val unavailVec = Wire(init = Vec.fill(nComponents){false.B})
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unavailVec := io.debugUnavail
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when (selectedHartReg >= nComponents.U) {
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when (selectedHartReg >= nComponents.U) {
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DMSTATUSRdData.allnonexistent := true.B
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DMSTATUSRdData.allnonexistent := true.B
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DMSTATUSRdData.anynonexistent := true.B
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DMSTATUSRdData.anynonexistent := true.B
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}.elsewhen (unavailVec(selectedHartReg)) {
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}.elsewhen (io.debugUnavail(selectedHartReg)) {
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DMSTATUSRdData.allunavail := true.B
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DMSTATUSRdData.allunavail := true.B
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DMSTATUSRdData.anyunavail := true.B
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DMSTATUSRdData.anyunavail := true.B
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}.elsewhen (haltedBitRegs(selectedHartReg)) {
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}.elsewhen (haltedBitRegs(selectedHartReg)) {
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