From f554ad7e2c8b77fce593e603d2a2c6275c7cdc34 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Mon, 27 Nov 2017 10:50:15 -0800 Subject: [PATCH] debug: Remove workaround for Chisel 3 #527 --- src/main/scala/devices/debug/Debug.scala | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index 353ecdfd..12dc7a4d 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -521,14 +521,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: DMSTATUSRdData.authenticated := true.B // Not implemented DMSTATUSRdData.version := 2.U // Version 0.13 - // Chisel3 Issue #527 , have to do intermediate assignment. - val unavailVec = Wire(init = Vec.fill(nComponents){false.B}) - unavailVec := io.debugUnavail - when (selectedHartReg >= nComponents.U) { DMSTATUSRdData.allnonexistent := true.B DMSTATUSRdData.anynonexistent := true.B - }.elsewhen (unavailVec(selectedHartReg)) { + }.elsewhen (io.debugUnavail(selectedHartReg)) { DMSTATUSRdData.allunavail := true.B DMSTATUSRdData.anyunavail := true.B }.elsewhen (haltedBitRegs(selectedHartReg)) {