remove zscale

.gitmodules

@@ -19,9 +19,6 @@
 [submodule "fpga-zynq"]
 	path = fpga-zynq
 	url = https://github.com/ucb-bar/fpga-zynq.git
-[submodule "zscale"]
-	path = zscale
-	url = https://github.com/ucb-bar/zscale
 [submodule "junctions"]
 	path = junctions
 	url = https://github.com/ucb-bar/junctions

.travis.yml

@@ -16,7 +16,6 @@ cache:
     rocket/target
     target
     uncore/target
-    zscale/target
 
 # packages needed to build riscv-tools
 addons:

Makefrag

@@ -22,7 +22,7 @@ CHISEL_ARGS := --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configN
 endif
 
 src_path = src/main/scala
-default_submodules = . junctions uncore hardfloat rocket zscale groundtest context-dependent-environments
+default_submodules = . junctions uncore hardfloat rocket groundtest context-dependent-environments
 chisel_srcs = $(addprefix $(base_dir)/,$(addsuffix /$(src_path)/*.scala,$(default_submodules) $(ROCKETCHIP_ADDONS)))
 
 disasm := 2>

emulator/Makefile

@@ -7,7 +7,6 @@ sim_dir = .
 output_dir = $(sim_dir)/output
 
 BACKEND = c
-#CONFIG ?= ZscaleConfig
 CONFIG ?= DefaultCPPConfig
 
 include $(base_dir)/Makefrag

project/build.scala

@@ -21,9 +21,8 @@ object BuildSettings extends Build {
   lazy val junctions  = project.dependsOn(chisel, cde)
   lazy val uncore     = project.dependsOn(junctions)
   lazy val rocket     = project.dependsOn(hardfloat, uncore)
-  lazy val zscale     = project.dependsOn(rocket)
   lazy val groundtest = project.dependsOn(rocket)
-  lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(zscale, groundtest)
+  lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(groundtest)
 
   lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
   lazy val make = inputKey[Unit]("trigger backend-specific makefile command")

regression/Makefile

@@ -70,7 +70,7 @@ fsim-asm-tests: stamps/$(CONFIG)/fsim-asm-tests.stamp
 fsim-bmark-tests: stamps/$(CONFIG)/fsim-bmark-tests.stamp
 fsim-torture: stamps/$(CONFIG)/fsim-torture-$(TORTURE_CONFIG).stamp
 
-submodule_names = chisel2 chisel3 context-dependent-environments dramsim2 firrtl groundtest hardfloat junctions rocket torture uncore zscale $(ROCKETCHIP_ADDONS)
+submodule_names = chisel2 chisel3 context-dependent-environments dramsim2 firrtl groundtest hardfloat junctions rocket torture uncore $(ROCKETCHIP_ADDONS)
 
 # Checks out all the rocket-chip submodules
 stamps/other-submodules.stamp:

src/main/scala/Configs.scala

@@ -7,7 +7,6 @@ import junctions._
 import uncore._
 import rocket._
 import rocket.Util._
-import zscale._
 import groundtest._
 import scala.math.max
 import DefaultTestSuites._
@@ -387,21 +386,6 @@ class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache
 
 class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
 
-class WithZscale extends Config(
-  (pname,site,here) => pname match {
-    case XLen => 32
-    case UseFPU => false
-    case BuildZscale => {
-      TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
-      TestGeneration.addSuites(List(zscaleBmarks))
-      (r: Bool, p: Parameters) => Module(new Zscale(r)(p))
-    }
-    case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
-    case DRAMCapacity => Dump("DRAM_CAPACITY", 64*1024*1024)
-    case _ => throw new CDEMatchError
-  }
-)
-
 class WithRV32 extends Config(
   (pname,site,here) => pname match {
     case XLen => 32
@@ -411,8 +395,6 @@ class WithRV32 extends Config(
   }
 )
 
-class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
-
 class FPGAConfig extends Config (
   (pname,site,here) => pname match {
     case NAcquireTransactors => 4

src/main/scala/Testing.scala

@@ -154,9 +154,6 @@ object DefaultTestSuites {
     List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az",
          "bb","bc","bf","bh","bj","bk","bm","bo","br","bs","ce","cf","cg","ci","ck","cl",
          "cm","cs","cv","cy","dc","df","dm","do","dr","ds","du","dv").map(_+"_matmul")): _*))
-
-  val zscaleBmarks = new BenchmarkTestSuite("zscale", "$(base_dir)/zscale/sw", LinkedHashSet(
-    "led", "mbist"))
 }
 
 object TestGenerator extends App with FileSystemUtilities {

src/main/scala/ZscaleChip.scala

@@ -1,77 +0,0 @@
-// See LICENSE for license details.
-
-package rocketchip
-
-import Chisel._
-import cde.{Parameters, Field}
-import junctions._
-import uncore._
-import rocket._
-import zscale._
-
-case object UseZscale extends Field[Boolean]
-case object BuildZscale extends Field[(Bool, Parameters) => Zscale]
-case object BootROMCapacity extends Field[Int]
-case object DRAMCapacity extends Field[Int]
-
-class ZscaleSystem(implicit p: Parameters)  extends Module {
-  val io = new Bundle {
-    val host = new HtifIO
-    val jtag = new HastiMasterIO().flip
-    val bootmem = new HastiSlaveIO().flip
-    val dram = new HastiSlaveIO().flip
-    val spi = new HastiSlaveIO().flip
-    val led = new PociIO
-    val corereset = new PociIO
-  }
-
-  val core = p(BuildZscale)(io.host.reset, p)
-
-  val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)
-
-  val sbus_afn = (addr: UInt) => addr(31, 29).orR
-  val dram_afn = (addr: UInt) => addr(31, 26) === UInt(8)
-  val spi_afn = (addr: UInt) => addr(31, 26) === UInt(9) && addr(25, 14) === UInt(0)
-
-  val pbus_afn = (addr: UInt) => addr(31) === UInt(1)
-  val led_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(0)
-  val corereset_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(1)
-
-  val xbar = Module(new HastiXbar(3, Seq(bootmem_afn, sbus_afn)))
-  val sadapter = Module(new HastiSlaveToMaster)
-  val sbus = Module(new HastiBus(Seq(dram_afn, spi_afn, pbus_afn)))
-  val padapter = Module(new HastiToPociBridge)
-  val pbus = Module(new PociBus(Seq(led_afn, corereset_afn)))
-
-  core.io.host <> io.host
-  xbar.io.masters(0) <> io.jtag
-  xbar.io.masters(1) <> core.io.dmem
-  xbar.io.masters(2) <> core.io.imem
-
-  io.bootmem <> xbar.io.slaves(0)
-  sadapter.io.in <> xbar.io.slaves(1)
-
-  sbus.io.master <> sadapter.io.out
-  io.dram <> sbus.io.slaves(0)
-  io.spi <> sbus.io.slaves(1)
-  padapter.io.in <> sbus.io.slaves(2)
-
-  pbus.io.master <> padapter.io.out
-  io.led <> pbus.io.slaves(0)
-  io.corereset <> pbus.io.slaves(1)
-}
-
-class ZscaleTop(topParams: Parameters) extends Module {
-  implicit val p = topParams.alterPartial({case TLId => "L1toL2" })
-  val io = new Bundle {
-    val host = new HtifIO
-  }
-
-  val sys = Module(new ZscaleSystem)
-  val bootmem = Module(new HastiSRAM(p(BootROMCapacity)/4))
-  val dram = Module(new HastiSRAM(p(DRAMCapacity)/4))
-
-  sys.io.host <> io.host
-  bootmem.io <> sys.io.bootmem
-  dram.io <> sys.io.dram
-}

vsrc/ZscaleTestHarness.v

@@ -1,95 +0,0 @@
-// See LICENSE for license details.
-//
-module ZscaleTestHarness;
-
-  reg clk   = 0;
-  reg reset = 1;
-
-  always #`CLOCK_PERIOD clk = ~clk;
-
-  wire        csr_resp_valid;
-  wire [31:0] dummy;
-  wire [31:0] csr_resp_bits;
-
-  ZscaleTop dut
-  (
-    .clk(clk),
-    .reset(reset),
-    .io_host_reset(reset),
-
-    .io_host_id(1'd0),
-    .io_host_csr_req_ready(),
-    .io_host_csr_req_valid(1'b1),
-    .io_host_csr_req_bits_rw(1'b0),
-    .io_host_csr_req_bits_addr(12'h780), // tohost register
-    .io_host_csr_req_bits_data({dummy, 32'd0}),
-    .io_host_csr_resp_ready(1'b1),
-    .io_host_csr_resp_valid(csr_resp_valid),
-    .io_host_csr_resp_bits({dummy, csr_resp_bits})
-  );
-
-  reg [1023:0] loadmem = 0;
-  reg [1023:0] vcdplusfile = 0;
-  reg [  63:0] max_cycles = 0;
-  reg [  63:0] trace_count = 0;
-  reg          verbose = 0;
-  wire         printf_cond = verbose && !reset;
-  integer      stderr = 32'h80000002;
-  integer      i;
-  reg [127:0]  image [8191:0];
-
-  initial
-  begin
-    $value$plusargs("max-cycles=%d", max_cycles);
-    verbose = $test$plusargs("verbose");
-    if ($value$plusargs("loadmem=%s", loadmem))
-    begin
-      $readmemh(loadmem, image);
-    end
-    if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
-    begin
-      $vcdplusfile(vcdplusfile);
-      $vcdpluson(0);
-      $vcdplusmemon(0);
-    end
-
-    #0.5;
-    for (i=0; i<`BOOT_CAPACITY/16; i=i+1) begin
-      dut.bootmem.ram.ram[4*i+0] = image[i][31:0];
-      dut.bootmem.ram.ram[4*i+1] = image[i][63:32];
-      dut.bootmem.ram.ram[4*i+2] = image[i][95:64];
-      dut.bootmem.ram.ram[4*i+3] = image[i][127:96];
-    end
-
-    #777.7 reset = 0;
-  end
-
-  reg [255:0] reason = 0;
-  always @(posedge clk)
-  begin
-    trace_count = trace_count + 1;
-
-    if (max_cycles > 0 && trace_count > max_cycles)
-      reason = "timeout";
-
-    if (!reset)
-    begin
-      if (csr_resp_valid && csr_resp_bits > 1)
-        $sformat(reason, "tohost = %d", csr_resp_bits >> 1);
-
-      if (csr_resp_valid && csr_resp_bits == 1)
-      begin
-        $vcdplusclose;
-        $finish;
-      end
-    end
-
-    if (reason)
-    begin
-      $fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
-      $vcdplusclose;
-      $finish;
-    end
-  end
-
-endmodule

zscale

@@ -1 +0,0 @@
-Subproject commit d430f0ae5bb5c32cc9d7f8c1743948667ac47246