remove zscale

src/main/scala/Configs.scala

@@ -7,7 +7,6 @@ import junctions._
 import uncore._
 import rocket._
 import rocket.Util._
-import zscale._
 import groundtest._
 import scala.math.max
 import DefaultTestSuites._
@@ -387,21 +386,6 @@ class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache
 
 class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
 
-class WithZscale extends Config(
-  (pname,site,here) => pname match {
-    case XLen => 32
-    case UseFPU => false
-    case BuildZscale => {
-      TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
-      TestGeneration.addSuites(List(zscaleBmarks))
-      (r: Bool, p: Parameters) => Module(new Zscale(r)(p))
-    }
-    case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
-    case DRAMCapacity => Dump("DRAM_CAPACITY", 64*1024*1024)
-    case _ => throw new CDEMatchError
-  }
-)
-
 class WithRV32 extends Config(
   (pname,site,here) => pname match {
     case XLen => 32
@@ -411,8 +395,6 @@ class WithRV32 extends Config(
   }
 )
 
-class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
-
 class FPGAConfig extends Config (
   (pname,site,here) => pname match {
     case NAcquireTransactors => 4

src/main/scala/Testing.scala

@@ -154,9 +154,6 @@ object DefaultTestSuites {
     List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az",
          "bb","bc","bf","bh","bj","bk","bm","bo","br","bs","ce","cf","cg","ci","ck","cl",
          "cm","cs","cv","cy","dc","df","dm","do","dr","ds","du","dv").map(_+"_matmul")): _*))
-
-  val zscaleBmarks = new BenchmarkTestSuite("zscale", "$(base_dir)/zscale/sw", LinkedHashSet(
-    "led", "mbist"))
 }
 
 object TestGenerator extends App with FileSystemUtilities {

src/main/scala/ZscaleChip.scala

@@ -1,77 +0,0 @@
-// See LICENSE for license details.
-
-package rocketchip
-
-import Chisel._
-import cde.{Parameters, Field}
-import junctions._
-import uncore._
-import rocket._
-import zscale._
-
-case object UseZscale extends Field[Boolean]
-case object BuildZscale extends Field[(Bool, Parameters) => Zscale]
-case object BootROMCapacity extends Field[Int]
-case object DRAMCapacity extends Field[Int]
-
-class ZscaleSystem(implicit p: Parameters)  extends Module {
-  val io = new Bundle {
-    val host = new HtifIO
-    val jtag = new HastiMasterIO().flip
-    val bootmem = new HastiSlaveIO().flip
-    val dram = new HastiSlaveIO().flip
-    val spi = new HastiSlaveIO().flip
-    val led = new PociIO
-    val corereset = new PociIO
-  }
-
-  val core = p(BuildZscale)(io.host.reset, p)
-
-  val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)
-
-  val sbus_afn = (addr: UInt) => addr(31, 29).orR
-  val dram_afn = (addr: UInt) => addr(31, 26) === UInt(8)
-  val spi_afn = (addr: UInt) => addr(31, 26) === UInt(9) && addr(25, 14) === UInt(0)
-
-  val pbus_afn = (addr: UInt) => addr(31) === UInt(1)
-  val led_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(0)
-  val corereset_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(1)
-
-  val xbar = Module(new HastiXbar(3, Seq(bootmem_afn, sbus_afn)))
-  val sadapter = Module(new HastiSlaveToMaster)
-  val sbus = Module(new HastiBus(Seq(dram_afn, spi_afn, pbus_afn)))
-  val padapter = Module(new HastiToPociBridge)
-  val pbus = Module(new PociBus(Seq(led_afn, corereset_afn)))
-
-  core.io.host <> io.host
-  xbar.io.masters(0) <> io.jtag
-  xbar.io.masters(1) <> core.io.dmem
-  xbar.io.masters(2) <> core.io.imem
-
-  io.bootmem <> xbar.io.slaves(0)
-  sadapter.io.in <> xbar.io.slaves(1)
-
-  sbus.io.master <> sadapter.io.out
-  io.dram <> sbus.io.slaves(0)
-  io.spi <> sbus.io.slaves(1)
-  padapter.io.in <> sbus.io.slaves(2)
-
-  pbus.io.master <> padapter.io.out
-  io.led <> pbus.io.slaves(0)
-  io.corereset <> pbus.io.slaves(1)
-}
-
-class ZscaleTop(topParams: Parameters) extends Module {
-  implicit val p = topParams.alterPartial({case TLId => "L1toL2" })
-  val io = new Bundle {
-    val host = new HtifIO
-  }
-
-  val sys = Module(new ZscaleSystem)
-  val bootmem = Module(new HastiSRAM(p(BootROMCapacity)/4))
-  val dram = Module(new HastiSRAM(p(DRAMCapacity)/4))
-
-  sys.io.host <> io.host
-  bootmem.io <> sys.io.bootmem
-  dram.io <> sys.io.dram
-}