riscv/rocket-chip
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fix pending_puts initialization

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This commit is contained in:
Yunsup Lee 2015-03-17 21:44:20 -07:00
parent 0e4cf74d8a
commit f4f59464df
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/cache.scala
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@ -810,7 +810,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
xact.data := UInt(0)
wmask_buffer.foreach { w => w := UInt(0) }
pending_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType),
UInt(0),
addPendingBitWhenHasData(io.inner.acquire),
SInt(-1, width = innerDataBeats)).toUInt
pending_reads := Mux(io.iacq().isSubBlockType(),
addPendingBitWhenWmaskIsNotFull(io.inner.acquire),