riscv/rocket-chip
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turn off fpu for default fpga config.

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a larger fpga can use defaultconfig
This commit is contained in:
Scott Beamer
2014-09-22 16:42:06 -07:00
committed by Yunsup Lee
parent fefa560017
commit f4e6cd75ab
1 changed files with 1 additions and 0 deletions
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src/main/scala/PublicConfigs.scala
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@@ -160,6 +160,7 @@ class FPGAConfig(default: ChiselConfig) extends ChiselConfig {
case "L1I" => 1 case "L1I" => 1
case "L1D" => Knob("L1D_WAYS") case "L1D" => Knob("L1D_WAYS")
} }
case BuildFPU => None
case FastMulDiv => false case FastMulDiv => false
case NITLBEntries => 4 case NITLBEntries => 4
case NBTBEntries => 8 case NBTBEntries => 8