diff --git a/src/main/scala/PublicConfigs.scala b/src/main/scala/PublicConfigs.scala
index c38b58f4..824779cc 100644
--- a/src/main/scala/PublicConfigs.scala
+++ b/src/main/scala/PublicConfigs.scala
@@ -160,6 +160,7 @@ class FPGAConfig(default: ChiselConfig) extends ChiselConfig {
         case "L1I" => 1
         case "L1D" => Knob("L1D_WAYS")
       }
+      case BuildFPU => None
       case FastMulDiv => false
       case NITLBEntries => 4
       case NBTBEntries => 8