rocketchip: match simulated memory width to ExtMem.beatBytes

src/main/scala/rocketchip/TestHarness.scala

@@ -7,11 +7,9 @@ import cde.{Parameters, Field}
 import junctions._
 import diplomacy._
 import coreplex._
-import junctions.NastiConstants._
-import util.LatencyPipe
+import uncore.axi4._
 
 case object BuildExampleTop extends Field[Parameters => ExampleTop[coreplex.BaseCoreplex]]
-case object SimMemLatency extends Field[Int]
 
 class TestHarness(q: Parameters) extends Module {
   val io = new Bundle {
@@ -24,79 +22,31 @@ class TestHarness(q: Parameters) extends Module {
     int := Bool(false)
 
   if (dut.io.mem_axi4.nonEmpty) {
-    val memSize = p(ExtMemSize)
+    val memSize = p(ExtMem).size
     require(memSize % dut.io.mem_axi4.size == 0)
-    for (axi <- dut.io.mem_axi4.map(_(0))) {
-      val mem = Module(new SimAXIMem(memSize / dut.io.mem_axi4.size))
-      mem.io.axi.ar <> axi.ar
-      mem.io.axi.aw <> axi.aw
-      mem.io.axi.w  <> axi.w
-      axi.r <> LatencyPipe(mem.io.axi.r, p(SimMemLatency))
-      axi.b <> LatencyPipe(mem.io.axi.b, p(SimMemLatency))
+    for (axi <- dut.io.mem_axi4) {
+      Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi
     }
   }
 
   val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug, io.success)
 
-  for (mmio_axi <- dut.io.mmio_axi) {
-    val slave = Module(new NastiErrorSlave)
-    slave.io <> mmio_axi
-  }
-
+  val mmio_sim = Module(LazyModule(new SimAXIMem(4096)).module)
+  mmio_sim.io.axi <> dut.io.mmio_axi
 }
 
-class SimAXIMem(size: BigInt)(implicit p: Parameters) extends NastiModule()(p) {
-  val io = new Bundle {
-    val axi = new NastiIO().flip
-  }
+class SimAXIMem(size: BigInt)(implicit p: Parameters) extends LazyModule {
+  val config = p(ExtMem)
 
-  val rValid = Reg(init = Bool(false))
-  val ar = RegEnable(io.axi.ar.bits, io.axi.ar.fire())
-  io.axi.ar.ready := !rValid
-  when (io.axi.ar.fire()) { rValid := Bool(true) }
-  when (io.axi.r.fire()) {
-    assert(ar.burst === NastiConstants.BURST_INCR)
-    ar.addr := ar.addr + (UInt(1) << ar.size)
-    ar.len := ar.len - UInt(1)
-    when (ar.len === UInt(0)) { rValid := Bool(false) }
-  }
+  val node = AXI4BlindInputNode(AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits)))))
+  val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
+  sram.node := AXI4Buffer()(AXI4Fragmenter(maxInFlight = 4)(node))
 
-  val w = io.axi.w.bits
-  require((size * 8) % nastiXDataBits == 0)
-  val depth = (size * 8) / nastiXDataBits
-  val mem = Mem(depth.toInt, w.data)
-
-  val wValid = Reg(init = Bool(false))
-  val bValid = Reg(init = Bool(false))
-  val aw = RegEnable(io.axi.aw.bits, io.axi.aw.fire())
-  io.axi.aw.ready := !wValid && !bValid
-  io.axi.w.ready := wValid
-  when (io.axi.b.fire()) { bValid := Bool(false) }
-  when (io.axi.aw.fire()) { wValid := Bool(true) }
-  when (io.axi.w.fire()) {
-    assert(aw.burst === NastiConstants.BURST_INCR)
-    aw.addr := aw.addr + (UInt(1) << aw.size)
-    aw.len := aw.len - UInt(1)
-    when (aw.len === UInt(0)) {
-      wValid := Bool(false)
-      bValid := Bool(true)
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val axi = node.bundleIn
     }
-
-    def row = mem((aw.addr >> log2Ceil(nastiXDataBits/8))(log2Ceil(depth)-1, 0))
-    val mask = FillInterleaved(8, w.strb)
-    val newData = mask & w.data | ~mask & row
-    row := newData
   }
-
-  io.axi.b.valid := bValid
-  io.axi.b.bits.id := aw.id
-  io.axi.b.bits.resp := RESP_OKAY
-
-  io.axi.r.valid := rValid
-  io.axi.r.bits.id := ar.id
-  io.axi.r.bits.data := mem((ar.addr >> log2Ceil(nastiXDataBits/8))(log2Ceil(depth)-1, 0))
-  io.axi.r.bits.resp := RESP_OKAY
-  io.axi.r.bits.last := ar.len === UInt(0)
 }
 
 class SimDTM(implicit p: Parameters) extends BlackBox {