riscv/rocket-chip
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rocketchip: match simulated memory width to ExtMem.beatBytes

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This commit is contained in:
Wesley W. Terpstra
2016-11-17 15:38:11 -08:00
parent 12d0d8bea2
commit f4ca5ea1f3
8 changed files with 41 additions and 124 deletions
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4
src/main/scala/groundtest/Tile.scala
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@ -5,7 +5,7 @@ import rocket._
import uncore.tilelink._
import uncore.agents.CacheName
import uncore.tilelink2._
import rocketchip.ExtMemBase
import rocketchip.ExtMem
import diplomacy._
import scala.util.Random
import scala.collection.mutable.ListBuffer
@ -30,7 +30,7 @@ trait HasGroundTestParameters {
val nUncached = tileSettings.uncached
val nCached = tileSettings.cached
val nPTW = tileSettings.ptw
val memStart = p(ExtMemBase)
val memStart = p(ExtMem).base
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
}