riscv/rocket-chip
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rocketchip: match simulated memory width to ExtMem.beatBytes

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This commit is contained in:
Wesley W. Terpstra
2016-11-17 15:38:11 -08:00
parent 12d0d8bea2
commit f4ca5ea1f3
8 changed files with 41 additions and 124 deletions
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4
src/main/scala/groundtest/Configs.scala
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@ -106,7 +106,7 @@ class WithComparator extends Config(
case BuildGroundTest =>
(p: Parameters) => Module(new ComparatorCore()(p))
case ComparatorKey => ComparatorParameters(
targets = Seq(site(ExtMemBase), testRamAddr),
targets = Seq(site(ExtMem).base, testRamAddr),
width = 8,
operations = 1000,
atomics = site(UseAtomics),
@ -136,7 +136,7 @@ class WithMemtest extends Config(
}
case GeneratorKey => TrafficGeneratorParameters(
maxRequests = 128,
startAddress = BigInt(site(ExtMemBase)))
startAddress = BigInt(site(ExtMem).base))
case BuildGroundTest =>
(p: Parameters) => Module(new GeneratorTest()(p))
case _ => throw new CDEMatchError