rocketchip: match simulated memory width to ExtMem.beatBytes

src/main/scala/groundtest/BusMasterTest.scala

@@ -21,7 +21,7 @@ class ExampleBusMaster(implicit val p: Parameters) extends Module
     with HasTileLinkParameters {
   val mmioParams = p.alterPartial({ case TLId => p(InnerTLId) })
   val memParams = p.alterPartial({ case TLId => p(OuterTLId) })
-  val memStart = p(ExtMemBase)
+  val memStart = p(ExtMem).base
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
 
   val io = new Bundle {
@@ -70,7 +70,7 @@ class BusMasterTest(implicit p: Parameters) extends GroundTest()(p)
        s_req_check :: s_resp_check :: s_done :: Nil) = Enum(Bits(), 8)
   val state = Reg(init = s_idle)
 
-  val busMasterBlock = p(ExtBusBase) >> p(CacheBlockOffsetBits)
+  val busMasterBlock = p(ExtBus).base >> p(CacheBlockOffsetBits)
   val start_acq = Put(
     client_xact_id = UInt(0),
     addr_block = UInt(busMasterBlock),

src/main/scala/groundtest/Configs.scala

@@ -106,7 +106,7 @@ class WithComparator extends Config(
     case BuildGroundTest =>
       (p: Parameters) => Module(new ComparatorCore()(p))
     case ComparatorKey => ComparatorParameters(
-      targets    = Seq(site(ExtMemBase), testRamAddr),
+      targets    = Seq(site(ExtMem).base, testRamAddr),
       width      = 8,
       operations = 1000,
       atomics    = site(UseAtomics),
@@ -136,7 +136,7 @@ class WithMemtest extends Config(
     }
     case GeneratorKey => TrafficGeneratorParameters(
       maxRequests = 128,
-      startAddress = BigInt(site(ExtMemBase)))
+      startAddress = BigInt(site(ExtMem).base))
     case BuildGroundTest =>
       (p: Parameters) => Module(new GeneratorTest()(p))
     case _ => throw new CDEMatchError

src/main/scala/groundtest/Regression.scala

@@ -20,7 +20,7 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
 
 abstract class Regression(implicit val p: Parameters)
     extends Module with HasTileLinkParameters with HasAddrMapParameters {
-  val memStart = p(ExtMemBase)
+  val memStart = p(ExtMem).base
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
   val io = new RegressionIO
 

src/main/scala/groundtest/TestHarness.scala

@@ -16,15 +16,10 @@ class TestHarness(q: Parameters) extends Module {
   io.success := dut.io.success
 
   if (dut.io.mem_axi4.nonEmpty) {
-    val memSize = p(ExtMemSize)
+    val memSize = p(ExtMem).size
     require(memSize % dut.io.mem_axi4.size == 0)
-    for (axi <- dut.io.mem_axi4.map(_(0))) {
-      val mem = Module(new SimAXIMem(memSize / dut.io.mem_axi4.size))
-      mem.io.axi.ar <> axi.ar
-      mem.io.axi.aw <> axi.aw
-      mem.io.axi.w  <> axi.w
-      axi.r <> LatencyPipe(mem.io.axi.r, p(SimMemLatency))
-      axi.b <> LatencyPipe(mem.io.axi.b, p(SimMemLatency))
+    for (axi <- dut.io.mem_axi4) {
+      Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi
     }
   }
 }

src/main/scala/groundtest/Tile.scala

@@ -5,7 +5,7 @@ import rocket._
 import uncore.tilelink._
 import uncore.agents.CacheName
 import uncore.tilelink2._
-import rocketchip.ExtMemBase
+import rocketchip.ExtMem
 import diplomacy._
 import scala.util.Random
 import scala.collection.mutable.ListBuffer
@@ -30,7 +30,7 @@ trait HasGroundTestParameters {
   val nUncached = tileSettings.uncached
   val nCached = tileSettings.cached
   val nPTW = tileSettings.ptw
-  val memStart = p(ExtMemBase)
+  val memStart = p(ExtMem).base
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
 }