riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

subsytem: change front bus buffer defaults (#1300)

Browse Source
This commit is contained in:
Henry Cook
2018-03-21 11:56:22 -07:00
committed by GitHub
parent 894960678c
commit f48c2767d7
2 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/subsystem/Ports.scala
View File

@ -130,7 +130,7 @@ trait HasSlaveAXI4Port { this: BaseSubsystem =>
id = IdRange(0, 1 << params.idBits))))))
private val fifoBits = 1
sbus.fromPort(Some(portName)) {
fbus.fromPort(Some(portName), buffers = 1) {
(TLWidthWidget(params.beatBytes)
:= AXI4ToTL()
:= AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))