riscv/rocket-chip
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make sure Cached generator comparison truncates to correct size

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This commit is contained in:
Howard Mao 2016-06-06 17:45:04 -07:00
parent 022503748e
commit f44778fa56
1 changed files with 10 additions and 1 deletions
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11
groundtest/src/main/scala/generator.scala
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@ -176,8 +176,17 @@ class HellaCacheGenerator(id: Int)
io.finished := (state === s_finished) io.finished := (state === s_finished)
def data_match(recv: Bits, expected: Bits): Bool = {
val recv_resized = Wire(Bits(width = genWordBits))
val exp_resized = Wire(Bits(width = genWordBits))
recv_resized := recv
exp_resized := expected
recv_resized === exp_resized
}
assert(!io.mem.resp.valid || !io.mem.resp.bits.has_data || assert(!io.mem.resp.valid || !io.mem.resp.bits.has_data ||
io.mem.resp.bits.data(genWordBits - 1, 0) === req_data, data_match(io.mem.resp.bits.data, req_data),
s"Received incorrect data in cached generator ${id}") s"Received incorrect data in cached generator ${id}")
} }