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fix TileLinkWidthAdapter

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This commit is contained in:
Howard Mao 2016-06-08 09:58:23 -07:00
parent 324cabc494
commit f421e2ab11
1 changed files with 155 additions and 157 deletions
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8
uncore/src/main/scala/converters.scala
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@ -756,7 +756,7 @@ object TileLinkWidthAdapter {
widener.io.in <> in
out <> widener.io.out
} else if (out.tlDataBits < in.tlDataBits) {
val narrower = Module(new TileLinkIOWidener(in.p(TLId), out.p(TLId)))
val narrower = Module(new TileLinkIONarrower(in.p(TLId), out.p(TLId)))
narrower.io.in <> in
out <> narrower.io.out
} else {
@ -961,9 +961,9 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
val outerMaxClients = outerParams.maxClientsPerPort
val outerIdBits = log2Up(outerParams.maxClientXacts * outerMaxClients)
require(outerDataBeats >= innerDataBeats)
require(outerDataBeats > innerDataBeats)
require(outerDataBeats % innerDataBeats == 0)
require(outerDataBits <= innerDataBits)
require(outerDataBits < innerDataBits)
require(outerDataBits * outerDataBeats == innerDataBits * innerDataBeats)
val factor = outerDataBeats / innerDataBeats
@ -973,7 +973,6 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
val out = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => outerTLId}))
}
if (factor > 1) {
val iacq = io.in.acquire.bits
val ognt = io.out.grant.bits
@ -1132,7 +1131,6 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
ignt_ctr.inc()
sending_get := Bool(false)
}
} else { io.out <> io.in }
}
class MMIOTileLinkManagerData(implicit p: Parameters)