riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

refactored dmem arbiter

Browse Source
This commit is contained in:
Yunsup Lee
2012-02-26 17:37:56 -08:00
parent 93f41d3359
commit f3bb02b2ea
3 changed files with 73 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
rocket/src/main/scala/consts.scala
View File

@ -164,9 +164,10 @@ object Constants
val PERM_BITS = 6;
// rocketNBDCache parameters
val DCACHE_PORTS = 2
val CPU_DATA_BITS = 64;
val CPU_TAG_BITS = 9;
val DCACHE_TAG_BITS = 1 + CPU_TAG_BITS;
val DCACHE_TAG_BITS = log2up(DCACHE_PORTS) + CPU_TAG_BITS
val OFFSET_BITS = 6; // log2(cache line size in bytes)
val NMSHR = 2; // number of primary misses
val NRPQ = 16; // number of secondary misses