riscv/rocket-chip
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allow configuration of rocket ICache buffering

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This commit is contained in:
Howard Mao 2015-12-02 17:18:39 -08:00
parent ebf2417a32
commit f35b83d3ca
2 changed files with 3 additions and 1 deletions
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2
rocket

@ -1 +1 @@
Subproject commit 57cc12f1b2f81708424c51c6a7d149b1c92372b6
Subproject commit b08f86b4fb9ef44d27ddda1b038e0d1cc15f0b24

2
src/main/scala/Configs.scala
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@ -89,6 +89,7 @@ class DefaultConfig extends Config (
case RowBits => findBy(CacheName)
case NTLBEntries => findBy(CacheName)
case CacheIdBits => findBy(CacheName)
case ICacheBufferWays => Knob("L1I_BUFFER_WAYS")
case "L1I" => {
case NSets => Knob("L1I_SETS") //64
case NWays => Knob("L1I_WAYS") //4
@ -207,6 +208,7 @@ class DefaultConfig extends Config (
case "L1D_WAYS" => 4
case "L1I_SETS" => 64
case "L1I_WAYS" => 4
case "L1I_BUFFER_WAYS" => false
}
)
class DefaultVLSIConfig extends DefaultConfig