riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix assignment of incoherent vector

Browse Source
This commit is contained in:
Howard Mao 2016-09-03 21:55:09 -07:00
parent a4c1942958
commit f34843f1b9
1 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/coreplex/Coreplex.scala
View File

@ -42,8 +42,6 @@ case object ExtraCoreplexPorts extends Field[Parameters => Bundle]
trait HasCoreplexParameters { trait HasCoreplexParameters {
implicit val p: Parameters implicit val p: Parameters
lazy val nTiles = p(NTiles) lazy val nTiles = p(NTiles)
lazy val nCachedTilePorts = p(NCachedTileLinkPorts)
lazy val nUncachedTilePorts = p(NUncachedTileLinkPorts)
lazy val nMemChannels = p(NMemoryChannels) lazy val nMemChannels = p(NMemoryChannels)
lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel) lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
lazy val nBanks = nMemChannels*nBanksPerMemChannel lazy val nBanks = nMemChannels*nBanksPerMemChannel
@ -115,7 +113,7 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
// Create point(s) of coherence serialization // Create point(s) of coherence serialization
val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)} val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
managerEndpoints.foreach { _.incoherent := Vec.fill(nCachedTilePorts)(Bool(false)) } managerEndpoints.flatMap(_.incoherent).foreach(_ := Bool(false))
val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({ val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
case TLId => "L1toL2" case TLId => "L1toL2"