riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

plic: Clean up comments and simplify checking

Browse Source
This commit is contained in:
Megan Wachs 2017-06-30 14:15:26 -07:00
parent 76f8de75e3
commit f31ae008f3
1 changed files with 4 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/main/scala/uncore/devices/Plic.scala
View File

@ -178,7 +178,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
// When a hart reads a claim/complete register, then the // When a hart reads a claim/complete register, then the
// device which is currently its highest priority is no longer pending. // device which is currently its highest priority is no longer pending.
// This code expolits the fact that, practically, only one claim/complete // This code exploits the fact that, practically, only one claim/complete
// register can be read at a time. We check for this because if the address map // register can be read at a time. We check for this because if the address map
// were to change, it may no longer be true. // were to change, it may no longer be true.
// Note: PLIC doesn't care which hart reads the register. // Note: PLIC doesn't care which hart reads the register.
@ -195,14 +195,13 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
// When a hart writes a claim/complete register, then // When a hart writes a claim/complete register, then
// the written device (as long as it is actually enabled for that // the written device (as long as it is actually enabled for that
// hart) is marked complete. // hart) is marked complete.
// This code expolits the fact that, practically, only one claim/complete register // This code exploits the fact that, practically, only one claim/complete register
// can be written at a time. We check for this because if the address map // can be written at a time. We check for this because if the address map
// were to change, it may no longer be true. // were to change, it may no longer be true.
// Note -- PLIC doesn't care which hart writes the register. // Note -- PLIC doesn't care which hart writes the register.
val completer = Wire(Vec(nHarts, Bool())) val completer = Wire(Vec(nHarts, Bool()))
assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot
val completerDev = Wire(UInt(width = log2Up(nDevices + 1))) val completerDev = Wire(UInt(width = log2Up(nDevices + 1)))
val checkCompleterDev = Wire(Vec(nHarts, UInt(width = log2Up(nDevices + 1)))) // For assertion purposes only.
val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), UInt(0)) val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), UInt(0))
(gateways zip completedDevs.toBools) foreach { case (g, c) => (gateways zip completedDevs.toBools) foreach { case (g, c) =>
g.complete := c g.complete := c
@ -217,19 +216,15 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
(Bool(true), maxDevs(i)) (Bool(true), maxDevs(i))
}, },
RegWriteFn { (valid, data) => RegWriteFn { (valid, data) =>
if (i > 0) { assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), "completerDev should be constant for all harts")
assert(checkCompleterDev(i-1) === data.extract(log2Ceil(nDevices+1)-1, 0))
}
checkCompleterDev(i) := data.extract(log2Ceil(nDevices+1)-1, 0)
completer(i) := valid && enables(i)(completerDev)
completerDev := data.extract(log2Ceil(nDevices+1)-1, 0) completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)
completer(i) := valid && enables(i)(completerDev)
Bool(true) Bool(true)
} }
) )
) )
} }
node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*) node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
priority(0) := 0 priority(0) := 0