From f31ae008f39afc0ae341987fb413365a617c88a0 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Fri, 30 Jun 2017 14:15:26 -0700
Subject: [PATCH] plic: Clean up comments and simplify checking

---
 src/main/scala/uncore/devices/Plic.scala | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/src/main/scala/uncore/devices/Plic.scala b/src/main/scala/uncore/devices/Plic.scala
index d6fff5dd..150b1db2 100644
--- a/src/main/scala/uncore/devices/Plic.scala
+++ b/src/main/scala/uncore/devices/Plic.scala
@@ -178,7 +178,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
 
     // When a hart reads a claim/complete register, then the
     // device which is currently its highest priority is no longer pending.
-    // This code expolits the fact that, practically, only one claim/complete
+    // This code exploits the fact that, practically, only one claim/complete
     // register can be read at a time. We check for this because if the address map
     // were to change, it may no longer be true.
     // Note: PLIC doesn't care which hart reads the register.
@@ -195,14 +195,13 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
     // When a hart writes a claim/complete register, then
     // the written device (as long as it is actually enabled for that
     // hart) is marked complete.
-    // This code expolits the fact that, practically, only one claim/complete register
+    // This code exploits the fact that, practically, only one claim/complete register
     // can be written at a time. We check for this because if the address map
     // were to change, it may no longer be true.
     // Note -- PLIC doesn't care which hart writes the register.
     val completer = Wire(Vec(nHarts, Bool()))
     assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot
     val completerDev = Wire(UInt(width = log2Up(nDevices + 1)))
-    val checkCompleterDev = Wire(Vec(nHarts, UInt(width = log2Up(nDevices + 1)))) // For assertion purposes only.
     val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), UInt(0))
     (gateways zip completedDevs.toBools) foreach { case (g, c) =>
        g.complete := c
@@ -217,19 +216,15 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
             (Bool(true), maxDevs(i))
           },
           RegWriteFn { (valid, data) =>
-            if (i > 0) {
-              assert(checkCompleterDev(i-1) === data.extract(log2Ceil(nDevices+1)-1, 0))
-            }
-            checkCompleterDev(i) := data.extract(log2Ceil(nDevices+1)-1, 0)
-            completer(i) := valid && enables(i)(completerDev)
+            assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), "completerDev should be constant for all harts")
             completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)
+            completer(i) := valid && enables(i)(completerDev)
             Bool(true)
           }
         )
       )
     }
 
-
     node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
 
     priority(0) := 0