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Merge pull request #296 from ucb-bar/split-unittest

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refactor unittest framework
This commit is contained in:
Yunsup Lee 2016-09-14 18:56:11 -07:00 committed by GitHub
commit f2cb9da91a
6 changed files with 71 additions and 68 deletions
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1
.travis.yml
View File

@ -35,6 +35,7 @@ env:
matrix:
- SUITE=RocketSuite
- SUITE=GroundtestSuite
- SUITE=UnittestSuite
# blacklist private branches
branches:

4
Makefrag
View File

@ -4,8 +4,8 @@ $(error Please set environment variable RISCV. Please take a look at README)
endif
MODEL ?= TestHarness
PROJECT := rocketchip
CFG_PROJECT := $(PROJECT)
PROJECT ?= rocketchip
CFG_PROJECT ?= $(PROJECT)
CXX ?= g++
CXXFLAGS := -O1

38
regression/Makefile
View File

@ -39,14 +39,20 @@ $(error Set SUITE to the regression suite you want to run)
endif
ifeq ($(SUITE),RocketSuite)
PROJECT=rocketchip
CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig TinyConfig
endif
ifeq ($(SUITE),GroundtestSuite)
PROJECT=rocketchip
CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtestConfig \
BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig \
UnitTestConfig
ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig
endif
ifeq ($(SUITE),UnittestSuite)
PROJECT=rocketchip.utest
CONFIGS=UnitTestConfig
endif
ifeq ($(SUITE), JtagDtmSuite)
@ -117,65 +123,65 @@ $(RISCV)/install.stamp:
# Builds the various simulators
stamps/%/emulator-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
date > $@
stamps/%/emulator-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV))
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
date > $@
stamps/%/emulator-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) debug
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
date > $@
stamps/%/vsim-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
date > $@
stamps/%/vsim-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV))
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
date > $@
stamps/%/vsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) debug
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
date > $@
# Runs tests on one of the simulators
stamps/%/emulator-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
date > $@
stamps/%/emulator-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
date > $@
stamps/%/emulator-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
$(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
date > $@
stamps/%/vsim-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
date > $@
stamps/%/vsim-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
date > $@
stamps/%/vsim-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
$(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
date > $@
# The torture tests run subtly differently on the different targets, so they

26
src/main/scala/coreplex/UnitTest.scala
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@ -1,26 +0,0 @@
package coreplex
import Chisel._
import unittest.UnitTestSuite
import rocket.Tile
import uncore.tilelink.TLId
import cde.Parameters
class UnitTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
require(tc.nSlaves == 0)
require(tc.nMemChannels == 0)
io.master.mmio.foreach { port =>
port.acquire.valid := Bool(false)
port.grant.ready := Bool(false)
}
io.debug.req.ready := Bool(false)
io.debug.resp.valid := Bool(false)
val l1params = p.alterPartial({ case TLId => "L1toL2" })
val tests = Module(new UnitTestSuite()(l1params))
override def hasSuccessFlag = true
io.success.get := tests.io.finished
}

24
src/main/scala/rocketchip/TestConfigs.scala
View File

@ -7,7 +7,6 @@ import uncore.tilelink._
import uncore.coherence._
import uncore.agents._
import uncore.devices.NTiles
import unittest._
import junctions._
import scala.collection.mutable.LinkedHashSet
import scala.collection.immutable.HashMap
@ -16,29 +15,6 @@ import scala.math.max
import coreplex._
import ConfigUtils._
class WithUnitTest extends Config(
(pname, site, here) => pname match {
case BuildCoreplex => {
val groundtest = if (site(XLen) == 64)
DefaultTestSuites.groundtest64
else
DefaultTestSuites.groundtest32
TestGeneration.addSuite(groundtest("p"))
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
(p: Parameters, c: CoreplexConfig) => Module(new UnitTestCoreplex(p, c))
}
case UnitTests => (testParams: Parameters) =>
JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
case NMemoryChannels => Dump("N_MEM_CHANNELS", 0)
case FPUKey => None
case UseAtomics => false
case UseCompressed => false
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case _ => throw new CDEMatchError
})
class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
class WithGroundTest extends Config(
(pname, site, here) => pname match {
case BuildCoreplex =>

46
src/main/scala/rocketchip/UnitTest.scala Normal file
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@ -0,0 +1,46 @@
// See LICENSE for license details.
package rocketchip.utest
import scala.collection.mutable.LinkedHashSet
import Chisel._
import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
import util.{ParameterizedBundle}
import rocket._
import uncore.tilelink._
import uncore.tilelink2.{LazyModule, LazyModuleImp}
import coreplex._
import rocketchip._
import unittest._
class WithUnitTest extends Config(
(pname, site, here) => pname match {
case UnitTests => (testParams: Parameters) => {
val groundtest = if (site(XLen) == 64)
DefaultTestSuites.groundtest64
else
DefaultTestSuites.groundtest32
TestGeneration.addSuite(groundtest("p"))
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
}
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case _ => throw new CDEMatchError
})
class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
class TestHarness(implicit val p: Parameters) extends Module {
val io = new Bundle {
val success = Bool(OUTPUT)
}
p(NCoreplexExtClients).assign(0)
p(ConfigString).assign("")
val l1params = p.alterPartial({ case TLId => "L1toL2" })
val tests = Module(new UnitTestSuite()(l1params))
io.success := tests.io.finished
}