riscv/rocket-chip
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better fpga configs

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This commit is contained in:
Scott Beamer
2014-09-23 17:05:14 -07:00
committed by Yunsup Lee
parent 4fe48f5a0a
commit f2ca887de3
1 changed files with 15 additions and 1 deletions
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16
src/main/scala/PublicConfigs.scala
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@@ -149,7 +149,21 @@ class DefaultConfig extends ChiselConfig {
class DefaultVLSIConfig extends DefaultConfig class DefaultVLSIConfig extends DefaultConfig
class DefaultCPPConfig extends DefaultConfig class DefaultCPPConfig extends DefaultConfig
class FPGAConfig(default: ChiselConfig) extends ChiselConfig { class FPGAConfig(default: ChiselConfig) extends ChiselConfig {
val topDefinitions:World.TopDefs = {
(pname,site,here) => pname match {
case UseBackupMemoryPort => false
case _ => default.topDefinitions(pname,site,here)
}
}
override val knobValues = default.knobValues
}
class DefaultFPGAConfig extends FPGAConfig(new DefaultConfig)
class FPGASmallConfig(default: ChiselConfig) extends ChiselConfig {
val topDefinitions:World.TopDefs = { val topDefinitions:World.TopDefs = {
(pname,site,here) => pname match { (pname,site,here) => pname match {
case NSets => site(CacheName) match { case NSets => site(CacheName) match {
@@ -180,4 +194,4 @@ class FPGAConfig(default: ChiselConfig) extends ChiselConfig {
} }
} }
class DefaultFPGAConfig extends FPGAConfig(new DefaultConfig) class DefaultFPGASmallConfig extends FPGASmallConfig(new FPGAConfig(new DefaultConfig))